fix(usb): the xHCI controller is found by class on any bus, sized, taken from the firmware, and 64-byte contexts laid out
boards/BRINGUP.md A1, FABRIC-3 SXL. It was matched by QEMU's own IDs on bus 0 alone, so no real board's was found. Now pci_find_class() reads every bus/slot/function; pci_bar_size() sizes BAR0; the USB Legacy Support capability hands the controller over from the BIOS, SMIs off; CSZ=1 contexts are placed 64 bytes apart instead of refused. XHCI_QEMU_ARGS lets QEMU place the controller as real hardware does. Test first: an NEC controller behind a PCIe root port -- no attach before, Zuse minted after, on all three ISAs. Standard acceptance unchanged; five hot-plugged identities attach. Not rehearsable: firmware handoff, CSZ=1. Still open: only the first controller found is used. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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Claude Opus 5.5
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@@ -538,9 +538,8 @@ int xhci_cmd_disable_slot(xhci_dev_t *dev, uint32_t slot_id);
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* is servicing (xHCI 1.2 spec table 7-13 speed IDs) -- used to pick EP0's
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* default Max Packet Size before any device descriptor has been read.
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*
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* Refuses (-2) if HCCPARAMS1.CSZ indicates 64-byte contexts -- only
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* 32-byte contexts are implemented (see xhci.h's own doc comment on
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* xhci_slot_ctx32_t).
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* Lays the contexts out 32 or 64 bytes apart, as HCCPARAMS1.CSZ says
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* (xhci.c's xhci_ctx_bytes(); 64-byte contexts refused until 2026-10-14).
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*
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* Called from xhci_poll_events()'s Command Completion handling once Enable
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* Slot succeeds -- not called directly by other code.
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