docs(v4): the ROMs' shared entries, and the mesh ROM as built
DATASHEET-F18.md lists all 19 entries of the host ROM, the six shared ones with the registers they use. MACHINE.md 2.2: built; 277 words, not the estimated 150-200; the system's words are address, push and ;. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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Claude Opus 5.5
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@@ -96,14 +96,40 @@ registers (§10.3).
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- **I/O addresses** (§10) sit inside the address space. A fetch from or store to one goes to
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the device, not to RAM. The exceptions are NODE-ERROR, which writes RAM and then traps, and
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the console receive addresses, where a store goes to RAM.
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- **ROM.** Built (2026-10-15; `MACHINE.md` §2): 2049 words of F18 code, `capsules/v4/rom`,
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assembled by `v4/tools/mkrom.c`. The machine starts at its entry 12 and assembles the
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system's source (`capsules/v4/sys`) from the console. It is a read-only range at
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- **ROM.** Built (2026-10-15; `MACHINE.md` §2): 2372 words of F18 code, `capsules/v4/rom`,
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assembled by `v4/tools/mkrom.c`. The machine starts at its entry 18 and assembles the
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system's source (`capsules/v4/sys`) from the console. A mesh node's ROM (`MACHINE.md` §2.2)
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is 277 words: entries 0–5, the shared math, and nothing else. It is a read-only range at
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`V4_NODE_WORDS` and above. It can be fetched and executed. A store there is an address fault.
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In the model it is attached by the owner, as every device is, and a reset detaches it.
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- Its routines are shared code, GA144-style (`MACHINE.md` 2.1). Payloads call them through
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the entry table at the ROM's base. Their state lives in a reserved RAM area. This sheet will
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list each entry's stack effect and the registers it uses once the ROM is built.
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the entry table at the ROM's base. Their state lives in a reserved RAM area. The entries:
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| Entry | Routine | Stack | Uses | In |
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|---|---|---|---|---|
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| 0 | `UM*` | ( u1 u2 -- ulo uhi ) | A | both ROMs |
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| 1 | `UM/MOD` | ( ulo uhi ud -- urem uquot ), exact for uhi < ud | A | both ROMs |
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| 2 | `D+` | ( d1 d2 -- d3 ) | — | both ROMs |
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| 3 | `DNEGATE` | ( d -- -d ) | — | both ROMs |
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| 4 | `Q.*` | ( a b -- c ), Q48.16 | A | both ROMs |
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| 5 | `Q./` | ( a b -- q ), Q48.16; by zero: D-11's result and error 11 | A, B; `(Q/)`'s 5 cells | both ROMs |
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| 6 | `(KEY)` | ( -- c ) | | host ROM |
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| 7 | `(TOKEN)` | ( -- len ) | | host ROM |
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| 8 | `(NUMBER)` | ( -- n flag ) | | host ROM |
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| 9 | `(FIND)` | ( -- rec \| 0 ) | | host ROM |
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| 10 | `(DEFINE)` | ( value kind -- ) | | host ROM |
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| 11 | `(OPCODE)` | ( -- op \| -1 ) | | host ROM |
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| 12 | `(OP)` | ( op -- ) | | host ROM |
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| 13 | `(LIT)` | ( v -- ) | | host ROM |
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| 14 | `(BRANCH)` | ( op target -- ) | | host ROM |
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| 15 | `(BRANCH>)` | ( op -- ref ) | | host ROM |
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| 16 | `(RESOLVE)` | ( ref target -- ) | | host ROM |
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| 17 | `(LABEL)` | ( -- addr ) | | host ROM |
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| 18 | `(ROM)`: where the host machine starts | | | host ROM |
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The list is `v4/include/v4/rom_entries.h` for entries 0–5 and `capsules/v4/rom/main.f18`
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for the rest. The assembler's routines (6–17) use A and B freely and keep their state in
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the ROM's area of the memory map; their registers are not yet listed one by one.
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## 6. Instruction word
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@@ -309,10 +335,10 @@ These are reported, not hidden:
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and it is not to be extended.
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2. **Device addresses are attached by the owner, not fixed.** D-4 (the memory map) is deferred.
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The FPGA needs fixed addresses.
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3. **The ROM** is built and the host node boots from it (2026-10-15). The ROM is the full
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assembler, about 2000 words, so it is the host node's. A mesh node's small loader ROM
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(the agreed correction, `JUSTIFICATION.md` §9) is not built yet. Until it is, a node that
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is born is sent the host's assembled system through its port.
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3. **The ROM** is built and the host node boots from it (2026-10-15). A mesh node's ROM is
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built too (`MACHINE.md` §2.2): entries 0–5, the shared math, and nothing else. In the test
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host a node Hera births carries it. The products have no births yet, so they do not link
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it. A node that is born is still sent the host's assembled system through its port.
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4. **`stack.h`'s opening comment** still says there is no overflow detection "and there never
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will be". D-16 revised that, and the header carries a revision note above it. The code
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counts and guards (§4). The comment's first paragraph is out of date.
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