Reorganize source tree: kernel/, v3/, v4/ split and board infrastructure

Source tree reorganization:
- Move StarForth v3 engine to v3/ (src/, include/, Makefile)
- Move kernel to kernel/ (src/, include/, linker/, Makefile)
- Create v4/ skeleton for F18-ISA golden model (DECOMPOSITION.md, JUSTIFICATION.md)
- Move FABRIC-0..4.md to docs/fabric/
- Move ONTOLOGY.md and ROADMAP.md to docs/

Board infrastructure:
- Add boards/ser5/, boards/raspi/, boards/milkv/, boards/zynq7020/
- Each board has board.mk (ISA, CPU flags, boot recipe) and README.md
- Root Makefile becomes thin dispatcher: boot_image, all, clean, docs take TARGET
- make boot_image TARGET=SER5|RASPI|MILKV builds one GPT/MBR image per board
- ZYNQ7020 target exists but stops with clear error (ARMv7 port not built yet)
- scripts/mkdiskimage.sh builds disk images for all boards

Docs pipeline:
- docs/book/ with LaTeX master (main.tex) and Makefile
- pandoc converts Markdown to LaTeX at build time
- Two Lua filters: table-widths.lua (wide tables wrap), code-breaks.lua (inline code breaks)
- make docs builds single PDF (754 pages, 0 missing characters)
- make docs TARGET=<board> adds board appendix
- build/docs/<book|board>/meta.tex stamps git commit into PDF

Bug fixes:
- 42 include paths that only worked by accident now use correct relative paths
- clang-18 hardcode replaced with configurable CC variable (fixed aarch64 build)
- Pi 5: kernel_2712.img linked at 0x80000, .bss zeroed, memory reserved
- Doxyfile, .clang-tidy, README.md, Kconfig paths updated

Verified:
- Hosted v3 build passes 1012 tests, 0 failures
- SER5 image boots in QEMU (OVMF), POST passes, K exact (65536 = Q48_ONE)
- Milk-V image boots in QEMU (OpenSBI + U-Boot + bootefi), POST passes
- make clean TARGET=<board> removes only that board and its ISA objects
- make all builds all boards, hosted v3, and docs in one run

Co-authored-by: Junie <junie@jetbrains.com>

kernel/include/starkernel/apic.h

@@ -0,0 +1,106 @@
+/*
+  StarForth — Steady-State Virtual Machine Runtime
+
+  Copyright (c) 2023–2025 Robert A. James
+  All rights reserved.
+
+  This file is part of the StarForth project.
+
+  Licensed under the StarForth License, Version 1.0 (the "License");
+  you may not use this file except in compliance with the License.
+
+  You may obtain a copy of the License at:
+      https://github.com/star.4th@proton.me/StarForth/LICENSE.txt
+
+  This software is provided "AS IS", WITHOUT WARRANTY OF ANY KIND,
+  express or implied, including but not limited to the warranties of
+  merchantability, fitness for a particular purpose, and noninfringement.
+
+ See the License for the specific language governing permissions and
+ limitations under the License.
+
+ StarForth — Steady-State Virtual Machine Runtime
+  Copyright (c) 2023–2025 Robert A. James
+  All rights reserved.
+
+  This file is part of the StarForth project.
+
+  Licensed under the StarForth License, Version 1.0 (the "License");
+  you may not use this file except in compliance with the License.
+
+  You may obtain a copy of the License at:
+       https://github.com/star.4th@proton.me/StarForth/LICENSE.txt
+
+  This software is provided "AS IS", WITHOUT WARRANTY OF ANY KIND,
+  express or implied, including but not limited to the warranties of
+  merchantability, fitness for a particular purpose, and noninfringement.
+
+  See the License for the specific language governing permissions and
+  limitations under the License.
+
+ */
+
+/**
+ * apic.h - Local APIC interface
+ */
+
+#ifndef STARKERNEL_APIC_H
+#define STARKERNEL_APIC_H
+
+#include "uefi.h"
+#include <stdint.h>
+
+/* Heartbeat timer vector (user-defined IRQ space starts at 0x20) */
+#define APIC_TIMER_VECTOR  0x20
+
+/* Spurious-interrupt vector (APIC_REG_SIVR, set in apic_init()). A normal,
+ * occasional hardware race per Intel SDM Vol.3 §10.9 -- not a fault. Must
+ * be silently ignored with no EOI. Surfaced by item 4.3.5's I/O APIC work:
+ * no real external interrupt had ever been delivered through the I/O APIC
+ * before, so this path was previously dormant. */
+#define APIC_SPURIOUS_VECTOR 0xFF
+
+/* Initialize Local APIC (enables APIC, sets spurious vector) */
+int apic_init(BootInfo *boot_info);
+
+/* Return this CPU's xAPIC ID (APIC_REG_ID bits 31:24) — used as the
+ * destination field when programming I/O APIC redirection entries. */
+uint8_t apic_id(void);
+
+/* Send End-of-Interrupt signal */
+void apic_eoi(void);
+
+/*
+ * Initialize APIC timer for periodic heartbeat.
+ * @param tsc_hz     TSC frequency in Hz (for calibration)
+ * @param tick_hz    Desired tick frequency (e.g., 100 = 100 Hz = 10ms period)
+ * @return 0 on success, -1 on failure
+ */
+int apic_timer_init(uint64_t tsc_hz, uint32_t tick_hz);
+
+/**
+ * Start the APIC timer (enables periodic interrupts).
+ * Call this after IDT and heartbeat handler are set up.
+ */
+void apic_timer_start(void);
+
+/**
+ * Stop the APIC timer (disables periodic interrupts).
+ */
+void apic_timer_stop(void);
+
+/**
+ * Re-arm the APIC timer at the current adaptive period (item 0.8, §26).
+ * Recomputes the initial count from heartbeat_next_period_ns() and writes
+ * it to the ICR; a periodic-mode ICR write restarts the countdown
+ * immediately at the new value. Called once per tick from the ISR, before
+ * heartbeat_tick().
+ */
+void apic_timer_rearm(void);
+
+/**
+ * Get the configured timer period in TSC ticks.
+ */
+uint64_t apic_timer_period_tsc(void);
+
+#endif /* STARKERNEL_APIC_H */