Robert Allan JamesandClaude Sonnet 5
986d042aa7
Fourth stage of the preemptive context-switching plan, and the biggest. LithosAnanke now genuinely, continuously preempts between Hera, Hermes, and Artemis -- timer-driven, running live for the entire remainder of every boot once the Tripod fleet registers, not a bounded probe. A real design fork was resolved before writing code: the naive approach (the timer ISR calling Stage 2's sk_vm_context_switch() directly) is broken -- Stage 0's trap frame lives on whatever stack was active at interrupt time, and jumping to a different stack via Stage 2's own independent swap mid-handler would abandon that trap frame unresumed, guaranteed corruption on the first tick. Chose the safer of two named options: the ISR only ever sets a flag and returns completely normally through its own full epilogue; the actual switch happens moments later, via Stage 2's already-proven mechanism, at a safe cooperative checkpoint on the mainline (execute_colon_word()'s per-word dispatch loop, checked on literally every word, not throttled to the existing 256-word heartbeat-tuning cadence) -- confirmed with the user that word-level granularity is fine-grained enough given the eventual Zynq FPGA target where a word is a mnemonic. New capsule_vm_switch_signal.c/.h: a purpose-built run-readiness signal, deliberately separate from capsule_vm_physics.c's execution-heat engine (that one's own header documents itself as never touched from interrupt context, by design). Slot table sized with headroom (8) rather than hardcoded to today's 3 participants, so extending participation later is another register() call, not a redesign -- per direct request to leave room for swapping the participant set. Simple linear accumulate-then- threshold for this first cut; a fancier law can replace it later without touching the mechanism around it. heartbeat_tick() gains its one deliberate, documented amendment to this file's own top-half/bottom-half discipline -- the first time this codebase reaches into VM-scheduling state from real ISR context. Registration happens only after all three VMs are fully born, right before the REPL starts -- no critical-section protection yet against being switched away mid-birth-setup. Known, flagged rough edge (not reconciled this pass): MSG-TICK's own idle-pump and this new mechanism can still independently move control between the same VMs; not observed to interact badly in verification, but not fully unified either. Verified interactively at the console on all 3 architectures with continuous background preemption running throughout -- amd64 computed `1 1 + .` -> 2, aarch64 computed `1 1 + dup DUP * . CR` -> 4, both correct, REPL fully responsive, zero fault indicators over sustained runtime. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_016UNhH1mhi52i6Qihh7ZV5S
src/starkernel/vm/
Kernel-side StarForth VM subsystem.
vm_core.c— kernel port of the core interpreter loop.vm_runtime.c— kernel VM runtime support.vm_bootstrap.c— kernel VM bootstrap (distinct frombootstrap/sk_vm_bootstrap.c, which owns the higher-level subsystem wiring called fromkernel_main.c).arena.c— capsule arena allocator (fixed-region allocation for capsule payload data).parity.c— birth/execution parity logging (VM ID + capsule hash + dictionary hash), enabling offline determinism verification.alloc_kernel.c— the kernel-side implementation of the VM's allocator interface actually referenced byMakefile.starkernel's build (seesrc/platform/README.mdfor a note on a second, unwired copy).q48_stubs.c— deliberate no-op stubs forq48_from_double()/q48_to_double()in the freestanding kernel build, where floating point is unavailable; always returns zero, safe because shared VM code only uses these results for logging/diagnostic paths that are inactive in the kernel build.vm_internal.h— internal-only declarations shared across this directory's files.
Subdirectories:
bootstrap/sk_vm_bootstrap.c— owns VM init + capsule loading wiring, called fromkernel_main.c;kernel_main.citself only owns hardware milestones.host/shim.c— host-service shim bridging the kernel VM tosrc/starkernel/hal/host_services.c.