Robert Allan JamesandClaude Sonnet 5
f43f3f4482
Punch list §25 item 0.4 complete. Adds aarch64_current_el() in arch.c: reads CurrentEL[3:2] on first call, caches the result (CurrentEL cannot change post-ExitBootServices, so every consumer gets the same answer without repeating the MRS). Called from arch_interrupts_init() in interrupts.c -- the earliest point with both a working console (up since M1) and a genuine first consumer (vector installation is the first EL-dependent operation) -- and the detected level is printed to the boot log there. Declared via extern-in-place in interrupts.c rather than added to the shared arch.h: "exception level" has no amd64/riscv64 equivalent, matching the convention already used for riscv64_timer_rearm() in item 0.3. Verified on real QEMU output: "AArch64: running at EL1", correctly positioned immediately before "IDT installed." in the serial log. Boots clean, dict_hash 0x3d4e1daf289da94f unchanged from the item 0.1-0.3 baseline. Scope: this item establishes the detection and exposes it; it does not yet change VBAR/ELR/SPSR or timer-register selection to use it. arch_interrupts_init() still writes VBAR_EL1 unconditionally, and now says so explicitly in its own doc comment -- if aarch64_current_el() ever reports 2 on real hardware, exceptions taken at EL2 vector through VBAR_EL2, which nothing programs yet. That gap is items 0.5 (vectors/saved-state) and 0.7 (CNTP vs CNTHP) to close, per FABRIC.md's GAP-B3 finding. The boot-log EL2 case prints a note pointing at both. Only aarch64-scoped files touched (arch.c, interrupts.c) -- no shared loader or header changed, so amd64 and riscv64 are provably unaffected; not rebuilt for this item. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
173 lines
6.3 KiB
C
173 lines
6.3 KiB
C
/*
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StarForth — Steady-State Virtual Machine Runtime
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Copyright (c) 2023–2025 Robert A. James. All rights reserved.
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Licensed under the StarForth License, Version 1.0.
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*/
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/**
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* arch.c (aarch64) - Architecture abstractions for StarKernel on AArch64
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*/
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#include "arch.h"
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#include <stdint.h>
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/* Installed by isr.S — installs VBAR_EL1 */
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extern void aarch64_install_vectors(void);
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/* -1 = not yet read. Cached rather than re-read on every call: CurrentEL
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* cannot change during the kernel's lifetime post-ExitBootServices, and a
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* cached value gives every consumer (vector install, GIC timer register
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* selection) the same answer without repeating the MRS. */
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static int s_current_el = -1;
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/**
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* @brief Return the AArch64 exception level the kernel is running at.
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*
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* Reads @c CurrentEL (bits [3:2] hold the EL number, [1:0] are RES0) on
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* first call and caches the result; every later call returns the cached
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* value. Safe to call at any point in boot, including before
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* @c console_init() — the read itself has no dependency, only the
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* printing of it does (see @c arch_interrupts_init() in @c interrupts.c,
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* the earliest point at which both this and a working console are
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* available).
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*
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* EDK2 on QEMU's aarch64 @c virt machine has been observed to leave the
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* kernel at either EL1 or EL2 depending on firmware build; nothing in this
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* tree may assume one over the other (FABRIC.md §25.7.1 GAP-B3). Every
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* EL-dependent choice — @c VBAR_EL1 vs @c VBAR_EL2, the @c ELR_ELx /
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* @c SPSR_ELx saved-state pair, and @c CNTP_*_EL0 vs @c CNTHP_*_EL2 — must
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* read this accessor rather than hardcode a level.
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*
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* @return 1 or 2. Never 0 or 3: a UEFI application that survived far enough
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* to reach this call cannot be running at EL0 (unprivileged) or EL3
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* (secure monitor — QEMU's virt firmware runs the kernel at EL1/EL2).
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*/
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int aarch64_current_el(void)
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{
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if (s_current_el < 0) {
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uint64_t current_el;
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__asm__ volatile ("mrs %0, CurrentEL" : "=r"(current_el));
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s_current_el = (int)((current_el >> 2) & 0x3);
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}
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return s_current_el;
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}
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/**
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* @brief Perform the earliest AArch64 architecture initialisation (no-op).
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*
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* On x86-64 this function loads the GDT; AArch64 has no equivalent because
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* privilege separation is provided by the exception-level architecture
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* (EL0/EL1/EL2/EL3) rather than segment descriptors. The exception vector
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* table is installed later in @c arch_interrupts_init() by calling
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* @c aarch64_install_vectors() which writes @c VBAR_EL1.
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*
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* This stub exists to satisfy the common @c arch_early_init() call site in
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* @c kernel_main() so that the same milestone sequence compiles across all
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* three supported ISAs (amd64 / aarch64 / riscv64).
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*/
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void arch_early_init(void)
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{
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/* No GDT on AArch64; privilege separation via exception levels.
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* Interrupt vectors installed later in arch_interrupts_init(). */
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}
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/**
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* @brief Enable IRQ delivery on the current core (AArch64 DAIFCLR).
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*
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* Issues @c MSR DAIFCLR, #2 which clears the @c I bit (IRQ mask) in the
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* @c DAIF (Debug / Abort / IRQ / FIQ) flags of the current exception level.
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* After this instruction the core will take IRQ exceptions from the GIC.
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* The @c memory clobber prevents the compiler from reordering stores across
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* the barrier.
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*
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* Must be called after @c arch_interrupts_init() has installed the vector
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* table in @c VBAR_EL1 and the GIC timer driver has been configured.
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*/
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void arch_enable_interrupts(void)
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{
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__asm__ volatile ("msr daifclr, #2" ::: "memory");
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}
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/**
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* @brief Disable IRQ delivery on the current core (AArch64 DAIFSET).
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*
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* Issues @c MSR DAIFSET, #2 which sets the @c I bit (IRQ mask) in the
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* @c DAIF flags, masking IRQ exceptions. FIQ, SError, and Debug exceptions
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* are unaffected. Used around critical sections in the single-threaded
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* kernel where interrupt delivery would corrupt shared state.
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*
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* The @c memory clobber acts as a compiler-level barrier; for a full
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* hardware memory barrier use @c DSB before calling this function.
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*/
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void arch_disable_interrupts(void)
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{
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__asm__ volatile ("msr daifset, #2" ::: "memory");
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}
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/**
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* @brief Halt the core until the next event (AArch64 WFI).
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*
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* Issues the @c WFI (Wait For Interrupt) instruction. The core enters a
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* low-power standby state and resumes execution when an IRQ, FIQ, SError,
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* debug event, or reset is detected. In the kernel panic path this is
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* called inside an infinite loop with interrupts disabled (@c DAIFSET)
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* to stop the processor permanently. In the idle path it reduces power
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* consumption between heartbeat ticks.
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*
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* The @c memory clobber prevents the compiler from sinking stores across
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* the @c WFI.
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*/
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void arch_halt(void)
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{
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__asm__ volatile ("wfi" ::: "memory");
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}
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void arch_cold_reset(void)
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{
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arch_disable_interrupts();
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/* PSCI SYSTEM_RESET (SMC64 function 0xC4000009) */
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__asm__ volatile (
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"mov x0, #0xC4000000\n"
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"movk x0, #0x0009\n"
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"smc #0\n"
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::: "x0", "memory"
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);
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for (;;) __asm__ volatile ("wfi" ::: "memory");
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}
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/**
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* @brief Read the AArch64 system counter (CNTPCT_EL0).
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*
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* Issues @c MRS @c %0, @c cntpct_el0 to read the 64-bit physical system
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* counter. On AArch64 the system counter is the architectural equivalent
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* of the x86-64 TSC: a monotonically incrementing clock whose frequency
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* is reported by @c CNTFRQ_EL0 and set by firmware at boot.
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*
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* Unlike @c RDTSC on x86-64, @c CNTPCT_EL0 is fully synchronised across
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* cores (no per-core skew), invariant across power-state changes, and
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* does not require serialisation for most measurement use cases. It is
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* used as the time base for @c timer_now_ns() and @c heartbeat_tick().
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*
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* @return Current 64-bit system counter value in counter ticks
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* (frequency given by @c CNTFRQ_EL0, typically 10–62.5 MHz).
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*/
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uint64_t arch_read_timestamp(void)
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{
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uint64_t val;
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__asm__ volatile ("mrs %0, cntpct_el0" : "=r"(val));
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return val;
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}
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/**
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* @brief Initialise the AArch64 MMU (stub — deferred to a later milestone).
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*
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* Full page-table setup (TTBR0/TTBR1, MAIR, TCR, SCTLR.M) is deferred to a
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* later milestone. This stub exists to satisfy the common @c arch_mmu_init()
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* call site shared across all three ISAs. The VMM subsystem (@c vmm.c)
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* handles page-table management independently of this hook.
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*/
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void arch_mmu_init(void)
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{
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/* Stub: MMU bring-up deferred for later milestone */
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}
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