Reorganize source tree: kernel/, v3/, v4/ split and board infrastructure
Source tree reorganization: - Move StarForth v3 engine to v3/ (src/, include/, Makefile) - Move kernel to kernel/ (src/, include/, linker/, Makefile) - Create v4/ skeleton for F18-ISA golden model (DECOMPOSITION.md, JUSTIFICATION.md) - Move FABRIC-0..4.md to docs/fabric/ - Move ONTOLOGY.md and ROADMAP.md to docs/ Board infrastructure: - Add boards/ser5/, boards/raspi/, boards/milkv/, boards/zynq7020/ - Each board has board.mk (ISA, CPU flags, boot recipe) and README.md - Root Makefile becomes thin dispatcher: boot_image, all, clean, docs take TARGET - make boot_image TARGET=SER5|RASPI|MILKV builds one GPT/MBR image per board - ZYNQ7020 target exists but stops with clear error (ARMv7 port not built yet) - scripts/mkdiskimage.sh builds disk images for all boards Docs pipeline: - docs/book/ with LaTeX master (main.tex) and Makefile - pandoc converts Markdown to LaTeX at build time - Two Lua filters: table-widths.lua (wide tables wrap), code-breaks.lua (inline code breaks) - make docs builds single PDF (754 pages, 0 missing characters) - make docs TARGET=<board> adds board appendix - build/docs/<book|board>/meta.tex stamps git commit into PDF Bug fixes: - 42 include paths that only worked by accident now use correct relative paths - clang-18 hardcode replaced with configurable CC variable (fixed aarch64 build) - Pi 5: kernel_2712.img linked at 0x80000, .bss zeroed, memory reserved - Doxyfile, .clang-tidy, README.md, Kconfig paths updated Verified: - Hosted v3 build passes 1012 tests, 0 failures - SER5 image boots in QEMU (OVMF), POST passes, K exact (65536 = Q48_ONE) - Milk-V image boots in QEMU (OpenSBI + U-Boot + bootefi), POST passes - make clean TARGET=<board> removes only that board and its ISA objects - make all builds all boards, hosted v3, and docs in one run Co-authored-by: Junie <junie@jetbrains.com>
This commit is contained in:
rajames
@@ -0,0 +1,17 @@
|
||||
# src/starkernel/arch/aarch64/
|
||||
|
||||
AArch64 architecture support for LithosAnanke.
|
||||
|
||||
- `arch.c` — architecture init entry point.
|
||||
- `apic.c` — GIC (Generic Interrupt Controller) stub, named `apic.c` to
|
||||
match the shared per-arch file-naming convention across
|
||||
amd64/aarch64/riscv64. Satisfies the common `apic_init()`/`apic_eoi()`
|
||||
call sites without real GIC bring-up yet; deferred to a later milestone.
|
||||
- `timer.c` — architected timer setup (heartbeat tick source).
|
||||
- `interrupts.c` — exception vector table setup and interrupt dispatch.
|
||||
- `boot.S` — early boot assembly.
|
||||
- `isr.S` — interrupt service routine stubs.
|
||||
|
||||
No `kernel_entry.S` — aarch64 uses a different UEFI loader entry path
|
||||
(`clang`/`lld-link` COFF target, since GCC cannot produce an aarch64 PE
|
||||
image; see `Makefile.starkernel`).
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,270 @@
|
||||
/*
|
||||
StarForth — Steady-State Virtual Machine Runtime
|
||||
Copyright (c) 2023–2025 Robert A. James. All rights reserved.
|
||||
Licensed under the StarForth License, Version 1.0.
|
||||
*/
|
||||
|
||||
/**
|
||||
* arch.c (aarch64) - Architecture abstractions for StarKernel on AArch64
|
||||
*/
|
||||
|
||||
#include "arch.h"
|
||||
#include "console.h"
|
||||
#include "starkernel/fdt.h"
|
||||
#include <stdint.h>
|
||||
|
||||
/* Installed by isr.S — installs VBAR_EL2 at EL2, VBAR_EL1 at EL1 (EL-aware
|
||||
* since before this comment was corrected, 2026-09-04 — see
|
||||
* interrupts.c's arch_interrupts_init() doc comment for the fuller
|
||||
* correction; this one-word staleness was caught in passing while fixing
|
||||
* that one). */
|
||||
extern void aarch64_install_vectors(void);
|
||||
|
||||
/* -1 = not yet read. Cached rather than re-read on every call: CurrentEL
|
||||
* cannot change during the kernel's lifetime post-ExitBootServices, and a
|
||||
* cached value gives every consumer (vector install, GIC timer register
|
||||
* selection) the same answer without repeating the MRS. */
|
||||
static int s_current_el = -1;
|
||||
|
||||
/**
|
||||
* @brief Return the AArch64 exception level the kernel is running at.
|
||||
*
|
||||
* Reads @c CurrentEL (bits [3:2] hold the EL number, [1:0] are RES0) on
|
||||
* first call and caches the result; every later call returns the cached
|
||||
* value. Safe to call at any point in boot, including before
|
||||
* @c console_init() — the read itself has no dependency, only the
|
||||
* printing of it does (see @c arch_interrupts_init() in @c interrupts.c,
|
||||
* the earliest point at which both this and a working console are
|
||||
* available).
|
||||
*
|
||||
* EDK2 on QEMU's aarch64 @c virt machine has been observed to leave the
|
||||
* kernel at either EL1 or EL2 depending on firmware build; nothing in this
|
||||
* tree may assume one over the other (FABRIC-0.md §25.7.1 GAP-B3). Every
|
||||
* EL-dependent choice — @c VBAR_EL1 vs @c VBAR_EL2, the @c ELR_ELx /
|
||||
* @c SPSR_ELx saved-state pair, and @c CNTP_*_EL0 vs @c CNTHP_*_EL2 — must
|
||||
* read this accessor rather than hardcode a level.
|
||||
*
|
||||
* @return 1 or 2. Never 0 or 3: a UEFI application that survived far enough
|
||||
* to reach this call cannot be running at EL0 (unprivileged) or EL3
|
||||
* (secure monitor — QEMU's virt firmware runs the kernel at EL1/EL2).
|
||||
*/
|
||||
int aarch64_current_el(void)
|
||||
{
|
||||
if (s_current_el < 0) {
|
||||
uint64_t current_el;
|
||||
__asm__ volatile ("mrs %0, CurrentEL" : "=r"(current_el));
|
||||
s_current_el = (int)((current_el >> 2) & 0x3);
|
||||
}
|
||||
return s_current_el;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Perform the earliest AArch64 architecture initialisation (no-op).
|
||||
*
|
||||
* On x86-64 this function loads the GDT; AArch64 has no equivalent because
|
||||
* privilege separation is provided by the exception-level architecture
|
||||
* (EL0/EL1/EL2/EL3) rather than segment descriptors. The exception vector
|
||||
* table is installed later in @c arch_interrupts_init() by calling
|
||||
* @c aarch64_install_vectors() which writes @c VBAR_EL1.
|
||||
*
|
||||
* This stub exists to satisfy the common @c arch_early_init() call site in
|
||||
* @c kernel_main() so that the same milestone sequence compiles across all
|
||||
* three supported ISAs (amd64 / aarch64 / riscv64).
|
||||
*/
|
||||
void arch_early_init(void)
|
||||
{
|
||||
/* No GDT on AArch64; privilege separation via exception levels.
|
||||
* Interrupt vectors installed later in arch_interrupts_init(). */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable IRQ delivery on the current core (AArch64 DAIFCLR).
|
||||
*
|
||||
* Issues @c MSR DAIFCLR, #2 which clears the @c I bit (IRQ mask) in the
|
||||
* @c DAIF (Debug / Abort / IRQ / FIQ) flags of the current exception level.
|
||||
* After this instruction the core will take IRQ exceptions from the GIC.
|
||||
* The @c memory clobber prevents the compiler from reordering stores across
|
||||
* the barrier.
|
||||
*
|
||||
* Must be called after @c arch_interrupts_init() has installed the vector
|
||||
* table in @c VBAR_EL1 and the GIC timer driver has been configured.
|
||||
*/
|
||||
void arch_enable_interrupts(void)
|
||||
{
|
||||
__asm__ volatile ("msr daifclr, #2" ::: "memory");
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable IRQ delivery on the current core (AArch64 DAIFSET).
|
||||
*
|
||||
* Issues @c MSR DAIFSET, #2 which sets the @c I bit (IRQ mask) in the
|
||||
* @c DAIF flags, masking IRQ exceptions. FIQ, SError, and Debug exceptions
|
||||
* are unaffected. Used around critical sections in the single-threaded
|
||||
* kernel where interrupt delivery would corrupt shared state.
|
||||
*
|
||||
* The @c memory clobber acts as a compiler-level barrier; for a full
|
||||
* hardware memory barrier use @c DSB before calling this function.
|
||||
*/
|
||||
void arch_disable_interrupts(void)
|
||||
{
|
||||
__asm__ volatile ("msr daifset, #2" ::: "memory");
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Halt the core until the next event (AArch64 WFI).
|
||||
*
|
||||
* Issues the @c WFI (Wait For Interrupt) instruction. The core enters a
|
||||
* low-power standby state and resumes execution when an IRQ, FIQ, SError,
|
||||
* debug event, or reset is detected. In the kernel panic path this is
|
||||
* called inside an infinite loop with interrupts disabled (@c DAIFSET)
|
||||
* to stop the processor permanently. In the idle path it reduces power
|
||||
* consumption between heartbeat ticks.
|
||||
*
|
||||
* The @c memory clobber prevents the compiler from sinking stores across
|
||||
* the @c WFI.
|
||||
*/
|
||||
void arch_halt(void)
|
||||
{
|
||||
__asm__ volatile ("wfi" ::: "memory");
|
||||
}
|
||||
|
||||
/* PSCI conduit selection (FABRIC-3.md §IV.3 item 7 fix, 2026-09-04).
|
||||
* Defaults to 0 (HVC) so a boot with no DTB -- this system's QEMU/UEFI
|
||||
* firmware, same `fdt_valid()` failure mode already documented in
|
||||
* apic.c's file header for GIC discovery -- keeps arch_cold_reset()'s
|
||||
* existing, working HVC behaviour unchanged. Set to 1 (SMC) by
|
||||
* aarch64_psci_conduit_init() below when the real DTB's own `/psci` node
|
||||
* says so. */
|
||||
static int s_psci_use_smc = 0;
|
||||
|
||||
/**
|
||||
* @brief Discover the real PSCI conduit ("smc" vs "hvc") from the DTB.
|
||||
*
|
||||
* Looks up the devicetree's PSCI firmware node and reads its `method`
|
||||
* property. BCM2712's own `/psci` node declares
|
||||
* `compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"` and
|
||||
* `method = "smc"` -- confirmed directly against `bcm2712.dtsi`, not
|
||||
* assumed. `fdt_find_node_by_compatible()` matches any entry in a node's
|
||||
* compatible list, so searching for just the first (most specific) string
|
||||
* is sufficient; the other two exist for older PSCI-spec-version
|
||||
* consumers, not because this node might be tagged differently.
|
||||
*
|
||||
* Leaves @c s_psci_use_smc at its default (0, HVC) if @p dtb is not a
|
||||
* valid FDT, no PSCI node is found, or `method` is anything other than
|
||||
* exactly `"smc"` -- including the explicit `"hvc"` case, and the
|
||||
* "property absent" case, both of which should keep the existing HVC
|
||||
* behaviour rather than guess.
|
||||
*
|
||||
* Called once from @c apic_init() (`arch/aarch64/apic.c`), the one point
|
||||
* in boot that already has @c boot_info->dtb in hand at the right time
|
||||
* for this kind of discovery (same rationale as that file's own GIC-base
|
||||
* lookup) -- collocated here in @c arch.c, not there, because
|
||||
* @c arch_cold_reset() is this function's actual consumer and has no
|
||||
* @c boot_info of its own to probe with by the time it runs (called from
|
||||
* deep in VM execution, via `BYE`). Same extern-in-place convention this
|
||||
* file and apic.c already use for @c aarch64_current_el().
|
||||
*
|
||||
* @param dtb Candidate devicetree blob (@c BootInfo->dtb); NULL-safe.
|
||||
*/
|
||||
void aarch64_psci_conduit_init(const void *dtb)
|
||||
{
|
||||
const void *node;
|
||||
const char *method;
|
||||
uint32_t len;
|
||||
|
||||
if (!fdt_valid(dtb)) {
|
||||
console_println("PSCI: no DTB -- using HVC (QEMU virt-machine default)");
|
||||
return;
|
||||
}
|
||||
|
||||
node = fdt_find_node_by_compatible(dtb, "arm,psci-1.0");
|
||||
if (!node) {
|
||||
console_println("PSCI: no DTB PSCI node -- using HVC (QEMU virt-machine default)");
|
||||
return;
|
||||
}
|
||||
|
||||
method = (const char *) fdt_find_prop_in_node(dtb, node, "method", &len);
|
||||
if (method && len >= 3 && method[0] == 's' && method[1] == 'm' && method[2] == 'c') {
|
||||
s_psci_use_smc = 1;
|
||||
console_println("PSCI: conduit discovered from DTB (method=\"smc\")");
|
||||
} else {
|
||||
console_println("PSCI: DTB method != \"smc\" -- using HVC");
|
||||
}
|
||||
}
|
||||
|
||||
void arch_cold_reset(void)
|
||||
{
|
||||
arch_disable_interrupts();
|
||||
/* PSCI SYSTEM_RESET (function 0x84000009). SYSTEM_RESET takes no
|
||||
* arguments and has no SMC64 variant defined by the PSCI spec -- only
|
||||
* the SMC32 encoding is valid (fixed 2026-08-18, was 0xC4000009).
|
||||
*
|
||||
* Conduit is @c s_psci_use_smc, set by @c aarch64_psci_conduit_init()
|
||||
* above from the real DTB when one is present (real Pi 5 hardware's
|
||||
* own `/psci` node declares `method = "smc"`, confirmed against
|
||||
* `bcm2712.dtsi`).
|
||||
*
|
||||
* FABRIC-1.md Section I, 2026-08-18: live gdb tracing (using the real
|
||||
* UEFI-relocated runtime address, not the standalone kernel.elf's
|
||||
* link-time address -- see that section for why those differ) proved
|
||||
* the SMC call itself traps on *this system's* QEMU aarch64 boot
|
||||
* (AAVMF UEFI firmware, no genuine EL3/TrustZone secure monitor, no
|
||||
* DTB forwarded to the guest either): PC does not fall through to the
|
||||
* wfi loop below, it jumps straight into this kernel's own exception
|
||||
* vector. PSCI there is served via HVC (hypervisor call, EL2)
|
||||
* instead -- exactly the @c s_psci_use_smc == 0 default case. The
|
||||
* function ID and calling convention are unchanged between conduits,
|
||||
* only the trapping instruction differs. */
|
||||
if (s_psci_use_smc) {
|
||||
__asm__ volatile (
|
||||
"mov x0, #0x84000000\n"
|
||||
"movk x0, #0x0009\n"
|
||||
"smc #0\n"
|
||||
::: "x0", "memory"
|
||||
);
|
||||
} else {
|
||||
__asm__ volatile (
|
||||
"mov x0, #0x84000000\n"
|
||||
"movk x0, #0x0009\n"
|
||||
"hvc #0\n"
|
||||
::: "x0", "memory"
|
||||
);
|
||||
}
|
||||
for (;;) __asm__ volatile ("wfi" ::: "memory");
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read the AArch64 system counter (CNTPCT_EL0).
|
||||
*
|
||||
* Issues @c MRS @c %0, @c cntpct_el0 to read the 64-bit physical system
|
||||
* counter. On AArch64 the system counter is the architectural equivalent
|
||||
* of the x86-64 TSC: a monotonically incrementing clock whose frequency
|
||||
* is reported by @c CNTFRQ_EL0 and set by firmware at boot.
|
||||
*
|
||||
* Unlike @c RDTSC on x86-64, @c CNTPCT_EL0 is fully synchronised across
|
||||
* cores (no per-core skew), invariant across power-state changes, and
|
||||
* does not require serialisation for most measurement use cases. It is
|
||||
* used as the time base for @c timer_now_ns() and @c heartbeat_tick().
|
||||
*
|
||||
* @return Current 64-bit system counter value in counter ticks
|
||||
* (frequency given by @c CNTFRQ_EL0, typically 10–62.5 MHz).
|
||||
*/
|
||||
uint64_t arch_read_timestamp(void)
|
||||
{
|
||||
uint64_t val;
|
||||
__asm__ volatile ("mrs %0, cntpct_el0" : "=r"(val));
|
||||
return val;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialise the AArch64 MMU (stub — deferred to a later milestone).
|
||||
*
|
||||
* Full page-table setup (TTBR0/TTBR1, MAIR, TCR, SCTLR.M) is deferred to a
|
||||
* later milestone. This stub exists to satisfy the common @c arch_mmu_init()
|
||||
* call site shared across all three ISAs. The VMM subsystem (@c vmm.c)
|
||||
* handles page-table management independently of this hook.
|
||||
*/
|
||||
void arch_mmu_init(void)
|
||||
{
|
||||
/* Stub: MMU bring-up deferred for later milestone */
|
||||
}
|
||||
@@ -0,0 +1,25 @@
|
||||
/*
|
||||
* boot.S (aarch64) - Entry stub and linker-script symbol substitutes.
|
||||
*
|
||||
* With lld-link (PE/COFF), GNU ld linker-script symbols are unavailable.
|
||||
* Define __text_start, __text_end, __kernel_start, __kernel_end here so
|
||||
* hal.c and pmm.c resolve. They all point to the image base, which is
|
||||
* sufficient for the monolithic loader build (UEFI manages page ownership).
|
||||
*
|
||||
* The .reloc section (PE base-relocation table) is generated automatically
|
||||
* by lld-link from the COFF relocations in the object files.
|
||||
*/
|
||||
.text
|
||||
.global __text_start
|
||||
.global __kernel_start
|
||||
__text_start:
|
||||
__kernel_start:
|
||||
|
||||
.global arch_bootstrap
|
||||
arch_bootstrap:
|
||||
ret
|
||||
|
||||
.global __text_end
|
||||
.global __kernel_end
|
||||
__text_end:
|
||||
__kernel_end:
|
||||
@@ -0,0 +1,223 @@
|
||||
/*
|
||||
StarForth — Steady-State Virtual Machine Runtime
|
||||
Copyright (c) 2023–2025 Robert A. James. All rights reserved.
|
||||
Licensed under the StarForth License, Version 1.0.
|
||||
*/
|
||||
|
||||
/**
|
||||
* interrupts.c (aarch64) - Exception vector setup and common handler
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include "arch.h"
|
||||
#include "console.h"
|
||||
#include "starkernel/timer.h"
|
||||
|
||||
volatile const char *g_sk_fault_word = (void *)0;
|
||||
|
||||
/* Defined in isr.S */
|
||||
extern void aarch64_install_vectors(void);
|
||||
|
||||
/* Defined in arch.c. Extern-declared here rather than in the shared arch.h:
|
||||
* "exception level" has no amd64/riscv64 equivalent, so it does not belong
|
||||
* in the cross-ISA header — same convention as riscv64_timer_rearm() in
|
||||
* arch/riscv64/interrupts.c. */
|
||||
extern int aarch64_current_el(void);
|
||||
|
||||
/* Defined in apic.c (items 0.6/0.7). Same extern-in-place convention: GICv2
|
||||
* and generic-timer register-level details belong to the file that owns
|
||||
* the MMIO base addresses / EL-aware register selection, not the shared
|
||||
* apic.h. */
|
||||
extern uint32_t apic_read_iar(void);
|
||||
extern uint32_t apic_timer_ppi(void);
|
||||
extern void apic_eoi_intid(uint32_t intid);
|
||||
extern void apic_timer_rearm(void);
|
||||
|
||||
/* Defined in virtio_input.c (item 4.3.5e). g_virtio_input_gic_intid is 0
|
||||
* (not a valid SPI INTID -- SPIs start at 32) until
|
||||
* virtio_input_find_keyboard() finds a real device and computes its routed
|
||||
* INTID, so this branch is inert on any boot where the device isn't
|
||||
* present. Same extern-in-place convention as the rest of this file. */
|
||||
extern uint32_t g_virtio_input_gic_intid;
|
||||
extern void virtio_input_isr(void);
|
||||
|
||||
/* INTID 1023 = "spurious" (GICv2 spec): the CPU interface has nothing
|
||||
* pending, typically because another interrupt at the same or higher
|
||||
* priority raced this one to acknowledgement. Architecturally defined,
|
||||
* not this board's invention, so it is named rather than left as a magic
|
||||
* number in the comparison below. */
|
||||
#define GIC_INTID_SPURIOUS 1023u
|
||||
|
||||
/**
|
||||
* @brief Dispatch an IRQ taken at current-EL with SPx (punch-list item 0.7).
|
||||
*
|
||||
* Called from @c irq_spx_trampoline in @c isr.S, which has already saved the
|
||||
* full caller-saved integer and FP/SIMD register sets plus @c ELR_ELx /
|
||||
* @c SPSR_ELx, and will restore all of it and @c ERET after this function
|
||||
* returns — unlike @c aarch64_exception_handler(), this path is designed to
|
||||
* return normally.
|
||||
*
|
||||
* Reads @c GICC_IAR once (the GICv2 acknowledgement step — this also moves
|
||||
* the interrupt to the active state), dispatches on the returned INTID, and
|
||||
* always completes with the matching @c GICC_EOIR write, spurious or not:
|
||||
* a spurious read must still not be treated as "nothing to clean up," and
|
||||
* an unrecognised real INTID still needs the CPU interface unblocked for
|
||||
* the next one.
|
||||
*
|
||||
* For the timer PPI (@c apic_timer_ppi() — 30 at EL1, 26 at EL2, decided
|
||||
* once in @c apic_init()): @c apic_timer_rearm() runs **first**, before
|
||||
* @c heartbeat_tick() — the ARM Generic Timer does not auto-reload, so
|
||||
* skipping this leaves the interrupt condition permanently latched (see
|
||||
* @c apic_timer_rearm()'s own doc comment). Ordering the re-arm ahead of
|
||||
* the rest of the dispatch means a fault in @c heartbeat_tick() cannot
|
||||
* also cost the next tick — same discipline as @c riscv64_timer_rearm()
|
||||
* (item 0.3).
|
||||
*
|
||||
* virtio-input (item 4.3.5e, @c g_virtio_input_gic_intid): dispatched
|
||||
* **before** the @c GICC_EOIR write below, not after — the ISR itself is
|
||||
* what deasserts the device's (level-triggered) interrupt line by reading
|
||||
* its ISR-status capability; EOI'ing first would let the GIC immediately
|
||||
* re-signal a still-asserted line. Same claim-dispatch-complete ordering
|
||||
* @c riscv64_interrupt_handler() uses for its own PLIC-routed devices.
|
||||
*/
|
||||
void aarch64_irq_handler(void)
|
||||
{
|
||||
uint32_t intid = apic_read_iar();
|
||||
|
||||
if (intid == apic_timer_ppi()) {
|
||||
apic_timer_rearm();
|
||||
heartbeat_tick();
|
||||
}
|
||||
|
||||
if (intid == g_virtio_input_gic_intid) {
|
||||
virtio_input_isr();
|
||||
}
|
||||
|
||||
if (intid != GIC_INTID_SPURIOUS) {
|
||||
apic_eoi_intid(intid);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Print a 64-bit value as "0xNNNNNNNNNNNNNNNN" to the kernel console.
|
||||
*
|
||||
* Formats @p val as a 16-nibble lowercase hex string preceded by "0x" into
|
||||
* a 19-byte stack buffer (including null terminator) then emits it via
|
||||
* @c console_puts(). Used by @c aarch64_exception_handler() to print
|
||||
* @c ESR_EL1, @c ELR_EL1, @c FAR_EL1, and @c SPSR_EL1 in the exception
|
||||
* diagnostic dump. No heap allocation or libc dependency.
|
||||
*
|
||||
* @param val 64-bit value to format.
|
||||
*/
|
||||
static void print_hex(uint64_t val)
|
||||
{
|
||||
char buf[19];
|
||||
buf[0] = '0'; buf[1] = 'x';
|
||||
for (int i = 15; i >= 0; i--) {
|
||||
int nibble = (int)(val & 0xF);
|
||||
buf[2 + i] = (char)(nibble < 10 ? '0' + nibble : 'a' + nibble - 10);
|
||||
val >>= 4;
|
||||
}
|
||||
buf[18] = '\0';
|
||||
console_puts(buf);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief AArch64 common exception handler — print diagnostic and spin.
|
||||
*
|
||||
* Called from the @c isr.S exception vector table stubs for all exception
|
||||
* types (synchronous, IRQ, FIQ, SError) that are not handled by a specific
|
||||
* driver. Reads the four key EL1 exception system registers directly:
|
||||
*
|
||||
* - @c ESR_EL1 — Exception Syndrome Register: encodes the exception class
|
||||
* (EC, bits [31:26]) and instruction-specific syndrome (ISS, bits [24:0]).
|
||||
* The EC identifies the cause (e.g., 0x21 = data abort from EL1, 0x25 =
|
||||
* data abort from EL0, 0x15 = SVC64).
|
||||
* - @c ELR_EL1 — Exception Link Register: the PC of the instruction that
|
||||
* caused the exception (or the instruction after, for IRQ/FIQ/SError).
|
||||
* - @c FAR_EL1 — Fault Address Register: the virtual address that triggered
|
||||
* a Data Abort or Instruction Abort; undefined for other exception types.
|
||||
* - @c SPSR_EL1 — Saved Program Status Register: the PSTATE at the time of
|
||||
* exception, including the mode field and interrupt-mask bits.
|
||||
*
|
||||
* Prints all four values to the kernel console then enters an infinite
|
||||
* @c WFE loop to halt the affected core permanently. All exceptions that
|
||||
* reach this handler are fatal — there is no recovery path.
|
||||
*
|
||||
* The global @c g_sk_fault_word is set by the VM FORTH dispatcher just
|
||||
* before calling each word's function pointer; it names the word executing
|
||||
* at the time of the fault, aiding post-mortem analysis from the serial log.
|
||||
* (Currently logged only on the amd64 #GP path; future AArch64 diagnostic
|
||||
* expansion can include it here.)
|
||||
*/
|
||||
void aarch64_exception_handler(void)
|
||||
{
|
||||
uint64_t esr, elr, far_val, spsr;
|
||||
__asm__ volatile ("mrs %0, esr_el1" : "=r"(esr));
|
||||
__asm__ volatile ("mrs %0, elr_el1" : "=r"(elr));
|
||||
__asm__ volatile ("mrs %0, far_el1" : "=r"(far_val));
|
||||
__asm__ volatile ("mrs %0, spsr_el1" : "=r"(spsr));
|
||||
|
||||
console_println("*** EXCEPTION (aarch64) ***");
|
||||
console_puts(" ESR_EL1 = "); print_hex(esr); console_puts("\n");
|
||||
console_puts(" ELR_EL1 = "); print_hex(elr); console_puts("\n");
|
||||
console_puts(" FAR_EL1 = "); print_hex(far_val); console_puts("\n");
|
||||
console_puts(" SPSR_EL1= "); print_hex(spsr); console_puts("\n");
|
||||
|
||||
for (;;) {
|
||||
__asm__ volatile ("wfe" ::: "memory");
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Install the AArch64 exception vector table (M4 milestone).
|
||||
*
|
||||
* First reads and reports the exception level via @c aarch64_current_el()
|
||||
* (punch-list item 0.4) — this is the earliest point in boot with both a
|
||||
* working console (up since M1) and a genuine need for the answer (vector
|
||||
* installation is the first EL-dependent operation). The read itself is
|
||||
* cheap and safe far earlier than this; only the console print is gated on
|
||||
* this call site.
|
||||
*
|
||||
* Then calls @c aarch64_install_vectors() (defined in @c isr.S) which
|
||||
* writes the address of the vector table base into @c VBAR_EL1 or
|
||||
* @c VBAR_EL2 (Vector Base Address Register), whichever matches the
|
||||
* exception level @c aarch64_current_el() just reported. After this
|
||||
* instruction all exceptions at that level (synchronous, IRQ, FIQ,
|
||||
* SError) dispatch through the 512-byte-aligned vector table assembled
|
||||
* in @c isr.S.
|
||||
*
|
||||
* **Correction, 2026-09-04 (FABRIC-3.md §IV.3 item 7's code audit):**
|
||||
* this doc comment and the runtime console message below previously
|
||||
* claimed EL2 was "a known gap... @c VBAR_EL1 is written unconditionally
|
||||
* regardless of the detected level," citing punch-list item 0.5 as the
|
||||
* still-open work to fix it. Checked against @c isr.S's own
|
||||
* @c aarch64_install_vectors() (the actual implementation, not this
|
||||
* comment) and found that claim stale: the assembly already branches on
|
||||
* @c aarch64_current_el() and writes @c vbar_el2 at EL2 /
|
||||
* @c vbar_el1 at EL1, threading the same answer through
|
||||
* @c el2_mode_flag for the IRQ trampoline's @c ELR_ELx/@c SPSR_ELx
|
||||
* selection too (see @c isr.S's own "EL selection" header comment).
|
||||
* There never was a gap here to close — item 0.5's EL2 vector work was
|
||||
* already done by the time this comment was written describing it as
|
||||
* open; only the comment was wrong, not the code.
|
||||
*
|
||||
* On AArch64 there is no IDT and no PIC to disable; the GIC replaces
|
||||
* both. The @c arch_interrupts_init() name is kept identical across all
|
||||
* ISAs so that @c kernel_main() can call the same symbol regardless of
|
||||
* the target architecture.
|
||||
*
|
||||
* Must be called after the kernel stack is established (so that the
|
||||
* correct-EL SP is valid) and before @c arch_enable_interrupts().
|
||||
*/
|
||||
void arch_interrupts_init(void)
|
||||
{
|
||||
int el = aarch64_current_el();
|
||||
console_puts("AArch64: running at EL");
|
||||
console_putc((char)('0' + el));
|
||||
console_println(el == 2
|
||||
? " (VBAR_EL2/CNTHP_*_EL2 -- both already EL-aware, see isr.S/apic.c)"
|
||||
: "");
|
||||
|
||||
aarch64_install_vectors();
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,97 @@
|
||||
/*
|
||||
* native_rpi5_entry.S (aarch64) - Raspberry Pi 5 native (non-UEFI) entry
|
||||
* stub (FABRIC-3.md §IV.3 item 1, 2026-09-04).
|
||||
*
|
||||
* **Never run on real hardware** -- the Pi 5 isn't in hand until
|
||||
* 2026-09-17 (FABRIC-3.md §II). Compile-only-verified.
|
||||
*
|
||||
* Entered directly by Pi 5 firmware at the classic bare-metal load address
|
||||
* 0x80000 (item 6, `config.txt`'s `os_check=0`, is still open -- that's
|
||||
* what actually gets a real image loaded there; this file is just the
|
||||
* code that would run once it is). No UEFI, no ACPI -- none of
|
||||
* `boot/uefi_loader.c`'s PE-loader shape applies on this path. Per
|
||||
* FABRIC-3.md §IV.1's own researched entry protocol:
|
||||
*
|
||||
* x0 = 32-bit DTB pointer, upper 32 bits of the 64-bit register
|
||||
* UNSPECIFIED -- must mask before use.
|
||||
* x1-x3 = reserved / zero, unused here.
|
||||
*
|
||||
* This stub's own job: mask and capture that DTB pointer into
|
||||
* `g_rpi5_dtb_ptr` (declared in `include/starkernel/rpi5_native_entry.h`),
|
||||
* establish a dedicated stack -- this path has no EDK2 boot stack to
|
||||
* inherit, there is no EDK2 at all here -- then tail-call
|
||||
* `rpi5_native_boot()` (`rpi5_native_boot.c`, §IV.3 item 2), which builds
|
||||
* `BootInfo` from the devicetree and calls the existing `kernel_main()`.
|
||||
* `rpi5_native_boot()` never returns; the `wfe`/`b` loop after the `bl`
|
||||
* exists only so this file's own control flow has somewhere defined to
|
||||
* go if that contract is ever violated.
|
||||
*
|
||||
* Build-system note: `kernel/Makefile`'s `KERNEL_ASM` wildcards every
|
||||
* `*.S` file in this directory into the kernel ELF build (not the PE/COFF
|
||||
* loader build -- that list is explicit, boot.S/isr.S/switch.S only), so
|
||||
* this file links into the ARCH=aarch64 QEMU/UEFI kernel ELF as dead
|
||||
* code, and is the entry point of the separately-linked Pi 5 native
|
||||
* image (`make boot_image TARGET=RASPI`):
|
||||
* `kernel/linker/starkernel-native-rpi5.ld` places `.text.entry` first
|
||||
* at 0x80000 and the image is flattened to `kernel_2712.img`.
|
||||
*
|
||||
* Pi 5 firmware loads only the file's bytes; `.bss` (NOLOAD) is whatever
|
||||
* was in RAM. It is zeroed here, before anything in it -- including
|
||||
* `g_rpi5_dtb_ptr` and this stub's own stack -- is used. x0 (the DTB
|
||||
* pointer) is preserved across the loop; only x4-x6 are touched.
|
||||
*/
|
||||
|
||||
.section .bss
|
||||
.align 8
|
||||
.global g_rpi5_dtb_ptr
|
||||
g_rpi5_dtb_ptr:
|
||||
.space 8 /* uint64_t -- masked DTB pointer */
|
||||
|
||||
.align 4
|
||||
g_rpi5_native_stack:
|
||||
.space 0x200000 /* 2 MiB, same convention as the
|
||||
* amd64/riscv64 kernel_entry.S
|
||||
* BSS stacks */
|
||||
g_rpi5_native_stack_top:
|
||||
|
||||
.section .text.entry, "ax"
|
||||
.global rpi5_native_start
|
||||
rpi5_native_start:
|
||||
/* Mask x0 to its documented 32-bit DTB-pointer range (§IV.1: the
|
||||
* upper 32 bits of the 64-bit register are unspecified by the
|
||||
* firmware's own entry protocol). */
|
||||
mov x1, #0xffffffff
|
||||
and x0, x0, x1
|
||||
|
||||
/* Zero .bss: [__bss_start, __bss_end), both 16-byte aligned by the
|
||||
* native linker script. */
|
||||
adrp x4, __bss_start
|
||||
add x4, x4, :lo12:__bss_start
|
||||
adrp x5, __bss_end
|
||||
add x5, x5, :lo12:__bss_end
|
||||
.Lbss_zero:
|
||||
cmp x4, x5
|
||||
b.hs .Lbss_done
|
||||
stp xzr, xzr, [x4], #16
|
||||
b .Lbss_zero
|
||||
.Lbss_done:
|
||||
|
||||
adrp x2, g_rpi5_dtb_ptr
|
||||
add x2, x2, :lo12:g_rpi5_dtb_ptr
|
||||
str x0, [x2]
|
||||
|
||||
/* Establish this path's own dedicated stack. */
|
||||
adrp x0, g_rpi5_native_stack_top
|
||||
add x0, x0, :lo12:g_rpi5_native_stack_top
|
||||
mov sp, x0
|
||||
|
||||
/* x0 was clobbered above for the stack-top address -- reload the
|
||||
* masked DTB pointer from g_rpi5_dtb_ptr before calling in. */
|
||||
adrp x0, g_rpi5_dtb_ptr
|
||||
add x0, x0, :lo12:g_rpi5_dtb_ptr
|
||||
ldr x0, [x0]
|
||||
bl rpi5_native_boot
|
||||
|
||||
.Lhalt:
|
||||
wfe
|
||||
b .Lhalt
|
||||
@@ -0,0 +1,93 @@
|
||||
/*
|
||||
StarForth — Steady-State Virtual Machine Runtime
|
||||
Copyright (c) 2023–2025 Robert A. James. All rights reserved.
|
||||
Licensed under the StarForth License, Version 1.0.
|
||||
*/
|
||||
|
||||
/**
|
||||
* rpi5_dtb.c - Raspberry Pi 5 (BCM2712) devicetree-based peripheral
|
||||
* discovery (FABRIC-3.md §IV.3, 2026-09-04).
|
||||
*
|
||||
* Confirmed directly against `bcm2712.dtsi` (raspberrypi/linux,
|
||||
* rpi-6.12.y) before writing this, not assumed:
|
||||
*
|
||||
* soc: soc@107c000000 {
|
||||
* compatible = "simple-bus";
|
||||
* ranges = <0x0 0x10 0x0 0x80000000>;
|
||||
* #address-cells = <1>;
|
||||
* #size-cells = <1>;
|
||||
* ...
|
||||
* uart10: serial@7d001000 {
|
||||
* compatible = "arm,pl011", "arm,primecell";
|
||||
* reg = <0x7d001000 0x200>;
|
||||
* };
|
||||
* mailbox: mailbox@7c013880 {
|
||||
* compatible = "brcm,bcm2835-mbox";
|
||||
* reg = <0x7c013880 0x40>;
|
||||
* };
|
||||
* };
|
||||
*
|
||||
* Every peripheral this file cares about lives under this one "soc"
|
||||
* node, which applies exactly one translation to every child `reg`
|
||||
* value: child address 0 maps to parent (CPU-physical) address
|
||||
* 0x10_0000_0000 (`ranges`'s own `<0x0 0x10 0x0 ...>` — child cell 0,
|
||||
* parent cells `0x10 0x0`, i.e. `0x10 << 32`). The child side's own
|
||||
* `#address-cells = <1>` confirms each `reg` value's first cell is the
|
||||
* whole child address (32-bit, no cell-splitting needed) before adding
|
||||
* the offset. `fdt.c`'s reader deliberately does not parse `ranges`
|
||||
* generally (it is "not a general devicetree library," per its own
|
||||
* header comment) — this one, fixed, SoC-wide offset is applied here
|
||||
* by name instead, since it is a single known hardware fact, not a
|
||||
* general mechanism this codebase needs elsewhere yet.
|
||||
*/
|
||||
|
||||
#include "starkernel/rpi5_dtb.h"
|
||||
#include "starkernel/fdt.h"
|
||||
|
||||
/* soc@107c000000's own `ranges` offset -- see this file's own doc
|
||||
* comment above for where it was confirmed. */
|
||||
#define BCM2712_SOC_RANGES_OFFSET 0x1000000000ULL
|
||||
|
||||
/**
|
||||
* @brief Read a devicetree `reg` property's first cell as big-endian.
|
||||
*
|
||||
* `fdt.c` keeps its own `be32()` helper file-local (freestanding, no
|
||||
* shared byte-swap utility to reuse) -- duplicated here rather than
|
||||
* exposing it, same "a few lines is simpler than a new shared
|
||||
* dependency" precedent `tools/pkcs8_ed25519.c` already set in this
|
||||
* codebase.
|
||||
*/
|
||||
static uint32_t reg_first_cell_be32(const unsigned char* b)
|
||||
{
|
||||
return ((uint32_t) b[0] << 24) | ((uint32_t) b[1] << 16) |
|
||||
((uint32_t) b[2] << 8) | (uint32_t) b[3];
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Find @p compatible's node, read its `reg` base address, and
|
||||
* apply the one fixed BCM2712 `soc`-node translation offset.
|
||||
*/
|
||||
static uint64_t rpi5_peripheral_base(const void* dtb, const char* compatible)
|
||||
{
|
||||
const void* node;
|
||||
const void* val;
|
||||
uint32_t len;
|
||||
|
||||
node = fdt_find_node_by_compatible(dtb, compatible);
|
||||
if (!node) return 0;
|
||||
|
||||
val = fdt_find_prop_in_node(dtb, node, "reg", &len);
|
||||
if (!val || len < 4) return 0;
|
||||
|
||||
return BCM2712_SOC_RANGES_OFFSET + reg_first_cell_be32((const unsigned char*) val);
|
||||
}
|
||||
|
||||
uint64_t rpi5_uart_base(const void* dtb)
|
||||
{
|
||||
return rpi5_peripheral_base(dtb, "arm,pl011");
|
||||
}
|
||||
|
||||
uint64_t rpi5_mailbox_base(const void* dtb)
|
||||
{
|
||||
return rpi5_peripheral_base(dtb, "brcm,bcm2835-mbox");
|
||||
}
|
||||
@@ -0,0 +1,237 @@
|
||||
/*
|
||||
StarForth — Steady-State Virtual Machine Runtime
|
||||
Copyright (c) 2023–2025 Robert A. James. All rights reserved.
|
||||
Licensed under the StarForth License, Version 1.0.
|
||||
*/
|
||||
|
||||
/**
|
||||
* rpi5_mailbox.c - VideoCore mailbox property-interface framebuffer
|
||||
* setup (FABRIC-3.md §IV.3 item 3, 2026-09-04).
|
||||
*
|
||||
* **Never run on real hardware** — the Pi 5 isn't in hand until
|
||||
* 2026-09-17 (FABRIC-3.md §II). Everything below is built from real,
|
||||
* cited sources rather than assumed, but is compile-only-verified.
|
||||
*
|
||||
* Register layout (offsets from `rpi5_mailbox_base()`, i.e. the
|
||||
* `mailbox` devicetree node's own translated base address —
|
||||
* `rpi5_dtb.c` already confirmed `0x107C013880` on real Pi 5
|
||||
* hardware, matching a Pi-5-specific bare-metal reference
|
||||
* (main.lv/writeup/raspberry5_baremetal_framebuffer.md) independently
|
||||
* confirming the same `0x107C000000` SoC base + `0x13880` mailbox
|
||||
* offset this codebase's own devicetree-driven lookup already
|
||||
* produces — two independent sources agreeing is why this offset is
|
||||
* trusted, not just cited once):
|
||||
*
|
||||
* +0x00 MBOX0_READ (receive: VC -> ARM)
|
||||
* +0x18 MBOX0_STATUS (bit30 MBOX_EMPTY: nothing to read)
|
||||
* +0x20 MBOX1_WRITE (send: ARM -> VC)
|
||||
* +0x38 MBOX1_STATUS (bit31 MBOX_FULL: cannot write yet)
|
||||
*
|
||||
* (`+0x20/+0x38` per the same Pi-5-specific reference above, which
|
||||
* treats MBOX0/MBOX1 as two structurally identical 0x20-byte blocks
|
||||
* back to back — a real difference from older-chip tutorials, which
|
||||
* often describe a single shared status register at `+0x18` for both
|
||||
* directions. Trusted here because it's the one source actually
|
||||
* confirmed against Pi 5 hardware, not an older SoC.)
|
||||
*
|
||||
* Message encoding (official wiki:
|
||||
* github.com/raspberrypi/firmware/wiki/Mailbox-property-interface,
|
||||
* channel and buffer format; property tag IDs/lengths from the same
|
||||
* page): write `(buffer_addr & ~0xF) | channel` to MBOX1_WRITE; read
|
||||
* back the same encoded value from MBOX0_READ once available, confirming
|
||||
* it before trusting the buffer (the response overwrites the request
|
||||
* in place — same shared buffer, not a separate response buffer). No
|
||||
* bus-address translation applied to the buffer pointer itself
|
||||
* (confirmed against the same Pi-5-specific reference: it writes the
|
||||
* plain masked pointer, no added GPU-bus-alias bit, unlike the
|
||||
* classic 32-bit-Pi convention some older tutorials describe) —
|
||||
* genuinely different per-SoC-generation behavior, not an oversight.
|
||||
*
|
||||
* Buffer/tag format (official wiki, same page): u32 total size, u32
|
||||
* request(0)/response(0x80000000|len) code, tags..., u32 end-tag(0).
|
||||
* Each tag: u32 id, u32 value-buffer size, u32 req-size/resp-flag,
|
||||
* value bytes padded to 4-byte alignment. Buffer itself must be
|
||||
* 16-byte aligned (only the upper 28 bits of its address travel
|
||||
* through the mailbox).
|
||||
*/
|
||||
|
||||
#include "starkernel/rpi5_mailbox.h"
|
||||
#include "starkernel/rpi5_dtb.h"
|
||||
|
||||
#define MBOX_OFF_READ 0x00u
|
||||
#define MBOX_OFF_STATUS0 0x18u
|
||||
#define MBOX_OFF_WRITE 0x20u
|
||||
#define MBOX_OFF_STATUS1 0x38u
|
||||
|
||||
#define MBOX_FULL 0x80000000u
|
||||
#define MBOX_EMPTY 0x40000000u
|
||||
|
||||
#define MBOX_CH_PROPERTY 8u
|
||||
|
||||
#define MBOX_CODE_REQUEST 0x00000000u
|
||||
#define MBOX_CODE_RESPONSE_OK 0x80000000u
|
||||
|
||||
#define TAG_SET_PHYS_SIZE 0x00048003u
|
||||
#define TAG_SET_VIRT_SIZE 0x00048004u
|
||||
#define TAG_SET_DEPTH 0x00048005u
|
||||
#define TAG_SET_PIXEL_ORDER 0x00048006u
|
||||
#define TAG_SET_VIRTUAL_OFFS 0x00048009u
|
||||
#define TAG_ALLOCATE_BUFFER 0x00040001u
|
||||
#define TAG_GET_PITCH 0x00040008u
|
||||
#define TAG_END 0x00000000u
|
||||
|
||||
#define PIXEL_ORDER_RGB 1u /* per the wiki's own tag doc: 0=BGR, 1=RGB */
|
||||
|
||||
/* 16-byte-aligned static request/response buffer -- no allocator
|
||||
* exists this early in boot (this driver runs before kmalloc's own
|
||||
* init, same as every other pre-M6 boot step), and one buffer is
|
||||
* enough: this driver only ever has one request in flight, never
|
||||
* concurrent. Exact word count for the 7-tag sequence below, counted
|
||||
* word-by-word (not estimated): 2 [header] + 5 [phys size] + 5 [virt
|
||||
* size] + 4 [depth] + 4 [pixel order] + 5 [virtual offset] + 5
|
||||
* [allocate] + 4 [get pitch] + 1 [end tag] = 35 words (140 bytes) --
|
||||
* 40 gives real margin without the array itself getting large enough
|
||||
* to matter. (An earlier version of this comment claimed 32 words was
|
||||
* "generous headroom" for a 38-word estimate against a 32-word array
|
||||
* -- that was wrong on its own terms before even being checked against
|
||||
* the real 35-word count; recomputed properly this time, not
|
||||
* re-estimated.) */
|
||||
static uint32_t g_mbox_buf[40] __attribute__((aligned(16)));
|
||||
|
||||
static inline void mmio_write32(uint64_t addr, uint32_t val)
|
||||
{
|
||||
*(volatile uint32_t*) addr = val;
|
||||
}
|
||||
|
||||
static inline uint32_t mmio_read32(uint64_t addr)
|
||||
{
|
||||
return *(volatile uint32_t*) addr;
|
||||
}
|
||||
|
||||
/* Appends one tag (id, value-buffer size in bytes, request size in
|
||||
* bytes, then `nvalues` u32 value words) to g_mbox_buf starting at
|
||||
* word index *idx, advancing *idx past it (including alignment
|
||||
* padding -- every value here is a whole number of u32 words already,
|
||||
* so no padding math is actually needed, but the wiki's own format
|
||||
* allows non-multiple-of-4 value sizes in general; this driver's own
|
||||
* tags never do). */
|
||||
static void append_tag(uint32_t* idx, uint32_t tag_id, uint32_t value_bytes,
|
||||
const uint32_t* values, uint32_t nvalues)
|
||||
{
|
||||
uint32_t i;
|
||||
g_mbox_buf[(*idx)++] = tag_id;
|
||||
g_mbox_buf[(*idx)++] = value_bytes;
|
||||
/* Request-size word: set equal to value_bytes (the value-buffer's
|
||||
* own size, which for TAG_ALLOCATE_BUFFER is 8 -- the response's
|
||||
* size, since the buffer must be big enough for whichever is
|
||||
* larger -- not the 4-byte true request payload). Common practice
|
||||
* across multiple reference implementations surveyed while writing
|
||||
* this, not a single spec-quoted number; firmware is not observed
|
||||
* to validate an exact match against the true request length.
|
||||
* Unverified against real hardware either way. */
|
||||
g_mbox_buf[(*idx)++] = value_bytes;
|
||||
for (i = 0; i < nvalues; i++) g_mbox_buf[(*idx)++] = values[i];
|
||||
}
|
||||
|
||||
int rpi5_mailbox_get_framebuffer(const void* dtb, uint32_t width, uint32_t height,
|
||||
uint32_t bpp, Rpi5FramebufferInfo* out)
|
||||
{
|
||||
uint64_t base;
|
||||
uint32_t idx;
|
||||
uint32_t send_val;
|
||||
uint32_t v2[2];
|
||||
|
||||
if (!out) return -1;
|
||||
|
||||
base = rpi5_mailbox_base(dtb);
|
||||
if (!base) return -2; /* mailbox node not found/malformed in the DTB */
|
||||
|
||||
idx = 2; /* words 0/1 are the header, filled in after tags are built */
|
||||
|
||||
v2[0] = width;
|
||||
v2[1] = height;
|
||||
append_tag(&idx, TAG_SET_PHYS_SIZE, 8, v2, 2);
|
||||
append_tag(&idx, TAG_SET_VIRT_SIZE, 8, v2, 2);
|
||||
|
||||
v2[0] = bpp;
|
||||
append_tag(&idx, TAG_SET_DEPTH, 4, v2, 1);
|
||||
|
||||
v2[0] = PIXEL_ORDER_RGB;
|
||||
append_tag(&idx, TAG_SET_PIXEL_ORDER, 4, v2, 1);
|
||||
|
||||
v2[0] = 0; v2[1] = 0; /* virtual offset x,y -- always (0,0), no scrolling support */
|
||||
append_tag(&idx, TAG_SET_VIRTUAL_OFFS, 8, v2, 2);
|
||||
|
||||
v2[0] = 16; /* alignment request, bytes */
|
||||
v2[1] = 0; /* response slot (base addr); request only sends v2[0] */
|
||||
append_tag(&idx, TAG_ALLOCATE_BUFFER, 8, v2, 2);
|
||||
|
||||
v2[0] = 0;
|
||||
append_tag(&idx, TAG_GET_PITCH, 4, v2, 1);
|
||||
|
||||
g_mbox_buf[idx++] = TAG_END;
|
||||
|
||||
g_mbox_buf[0] = idx * 4u; /* total buffer size, bytes */
|
||||
g_mbox_buf[1] = MBOX_CODE_REQUEST;
|
||||
|
||||
send_val = ((uint32_t) (uintptr_t) g_mbox_buf & ~0xFu) | MBOX_CH_PROPERTY;
|
||||
|
||||
while ((mmio_read32(base + MBOX_OFF_STATUS1) & MBOX_FULL) != 0)
|
||||
{ /* spin until MBOX1 (send) has room */
|
||||
}
|
||||
mmio_write32(base + MBOX_OFF_WRITE, send_val);
|
||||
|
||||
for (;;)
|
||||
{
|
||||
while ((mmio_read32(base + MBOX_OFF_STATUS0) & MBOX_EMPTY) != 0)
|
||||
{ /* spin until MBOX0 (receive) has a message */
|
||||
}
|
||||
if (mmio_read32(base + MBOX_OFF_READ) == send_val) break;
|
||||
/* A message arrived, but not the one we sent (another channel's
|
||||
* traffic) -- discard and keep waiting, per the wiki's own
|
||||
* documented channel-matching convention. */
|
||||
}
|
||||
|
||||
if (g_mbox_buf[1] != MBOX_CODE_RESPONSE_OK) return -3; /* VC rejected the request */
|
||||
|
||||
/* Re-walk the tags to pull out the allocate-buffer and get-pitch
|
||||
* responses -- same fixed order they were sent in, so fixed word
|
||||
* offsets are safe to compute directly rather than re-parsing
|
||||
* generically (this driver only ever sends this one sequence). */
|
||||
{
|
||||
uint32_t alloc_tag_value_off = 2 /* header */
|
||||
+ (3 + 2) /* phys size */
|
||||
+ (3 + 2) /* virt size */
|
||||
+ (3 + 1) /* depth */
|
||||
+ (3 + 1) /* pixel order */
|
||||
+ (3 + 2) /* virtual offset */
|
||||
+ 3; /* allocate-buffer tag header, then its value words */
|
||||
uint32_t pitch_tag_value_off = alloc_tag_value_off + 2 /* alloc response: base+size */
|
||||
+ 3; /* get-pitch tag header, then its value word */
|
||||
|
||||
uint32_t fb_addr = g_mbox_buf[alloc_tag_value_off];
|
||||
uint32_t fb_size = g_mbox_buf[alloc_tag_value_off + 1];
|
||||
uint32_t pitch_bytes = g_mbox_buf[pitch_tag_value_off];
|
||||
|
||||
if (fb_addr == 0 || fb_size == 0 || pitch_bytes == 0) return -4;
|
||||
|
||||
/* Allocate-buffer's own response address is a VC bus address,
|
||||
* not necessarily the plain ARM-physical one -- masking the
|
||||
* top bits to recover the ARM-physical alias is the documented
|
||||
* convention on earlier Pi chips; kept here defensively even
|
||||
* though the Pi-5-specific reference this file cites for the
|
||||
* *send* side found no bus-alias bit in play there. Genuinely
|
||||
* unverified which of these is correct for Pi 5's own
|
||||
* allocate-buffer response specifically -- flagged, not
|
||||
* guessed past this comment. */
|
||||
out->base = (void*) (uintptr_t) (fb_addr & 0x3FFFFFFFu);
|
||||
out->size = fb_size;
|
||||
out->width = width;
|
||||
out->height = height;
|
||||
out->pixels_per_scanline = pitch_bytes / (bpp / 8u);
|
||||
out->pixel_format = 0; /* PixelRedGreenBlueReserved8BitPerColor --
|
||||
* matches PIXEL_ORDER_RGB requested above */
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,105 @@
|
||||
/*
|
||||
* switch.S (aarch64) - Cooperative VM context switch primitive.
|
||||
*
|
||||
* FABRIC-3.md §XXVIII (Stage 2, preemptive-context-switch save/restore
|
||||
* primitive, 2026-09-13). Deliberately NOT isr.S's interrupt trap frame
|
||||
* (Stage 0) -- that saves everything because an interrupt has no call
|
||||
* site. sk_vm_switch_to() is an ordinary `bl`, so AAPCS64 already makes
|
||||
* every caller-saved register (x0-x18, v0-v7, v16-v31) the caller's own
|
||||
* problem across the call. Only the callee-saved set needs explicit
|
||||
* handling: x19-x28, x29 (fp), x30 (lr), and d8-d15 (only the low 64
|
||||
* bits of v8-v15 are callee-saved per AAPCS64).
|
||||
*
|
||||
* void sk_vm_switch_to(uint64_t *save_sp_out, uint64_t new_sp);
|
||||
* x0 = save_sp_out, x1 = new_sp
|
||||
*
|
||||
* For a VM that has never run before, new_sp must point at a synthetic
|
||||
* 160-byte frame built by the C glue (switch.c) to this exact layout,
|
||||
* with x30 (lr) set to the trampoline entry address and everything else
|
||||
* zeroed, so the final `ret` below (which branches to lr) jumps there.
|
||||
*/
|
||||
|
||||
.section .text
|
||||
.balign 4
|
||||
|
||||
.equ SW_X19, 0
|
||||
.equ SW_X21, 16
|
||||
.equ SW_X23, 32
|
||||
.equ SW_X25, 48
|
||||
.equ SW_X27, 64
|
||||
.equ SW_X29, 80 /* x29 (fp), x30 (lr) */
|
||||
.equ SW_D8, 96
|
||||
.equ SW_D10, 112
|
||||
.equ SW_D12, 128
|
||||
.equ SW_D14, 144
|
||||
.equ SW_SIZE, 160
|
||||
|
||||
/* .hidden is an ELF-only visibility directive with no COFF equivalent;
|
||||
* this file is also assembled for the aarch64 loader, which clang targets
|
||||
* at aarch64-pc-windows-msvc (PE/COFF) -- guard on _WIN32 (defined only by
|
||||
* that target), matching isr.S's own precedent exactly. */
|
||||
#ifndef _WIN32
|
||||
.hidden sk_vm_switch_to
|
||||
#endif
|
||||
|
||||
.global sk_vm_switch_to
|
||||
sk_vm_switch_to:
|
||||
sub sp, sp, #SW_SIZE
|
||||
|
||||
stp x19, x20, [sp, #SW_X19]
|
||||
stp x21, x22, [sp, #SW_X21]
|
||||
stp x23, x24, [sp, #SW_X23]
|
||||
stp x25, x26, [sp, #SW_X25]
|
||||
stp x27, x28, [sp, #SW_X27]
|
||||
stp x29, x30, [sp, #SW_X29]
|
||||
stp d8, d9, [sp, #SW_D8]
|
||||
stp d10, d11, [sp, #SW_D10]
|
||||
stp d12, d13, [sp, #SW_D12]
|
||||
stp d14, d15, [sp, #SW_D14]
|
||||
|
||||
mov x2, sp
|
||||
str x2, [x0] /* *save_sp_out = sp (this context's parked SP) */
|
||||
|
||||
mov sp, x1 /* sp = new_sp (switch stacks) */
|
||||
|
||||
ldp x19, x20, [sp, #SW_X19]
|
||||
ldp x21, x22, [sp, #SW_X21]
|
||||
ldp x23, x24, [sp, #SW_X23]
|
||||
ldp x25, x26, [sp, #SW_X25]
|
||||
ldp x27, x28, [sp, #SW_X27]
|
||||
ldp x29, x30, [sp, #SW_X29]
|
||||
ldp d8, d9, [sp, #SW_D8]
|
||||
ldp d10, d11, [sp, #SW_D10]
|
||||
ldp d12, d13, [sp, #SW_D12]
|
||||
ldp d14, d15, [sp, #SW_D14]
|
||||
|
||||
add sp, sp, #SW_SIZE
|
||||
ret
|
||||
|
||||
/*
|
||||
* uint64_t sk_vm_switch_prime(uint64_t stack_top, void *entry);
|
||||
*
|
||||
* Builds the synthetic frame above at the top of a fresh native stack, so
|
||||
* the first ever sk_vm_switch_to() into it lands at `entry` (x30/lr) via
|
||||
* its final `ret`. Kept in this file (not C) so the layout can never
|
||||
* drift from sk_vm_switch_to() above -- one set of offsets, not two.
|
||||
*/
|
||||
#ifndef _WIN32
|
||||
.hidden sk_vm_switch_prime
|
||||
#endif
|
||||
|
||||
.global sk_vm_switch_prime
|
||||
sk_vm_switch_prime:
|
||||
sub x2, x0, #SW_SIZE
|
||||
stp xzr, xzr, [x2, #SW_X19]
|
||||
stp xzr, xzr, [x2, #SW_X21]
|
||||
stp xzr, xzr, [x2, #SW_X23]
|
||||
stp xzr, xzr, [x2, #SW_X25]
|
||||
stp xzr, xzr, [x2, #SW_X27]
|
||||
stp xzr, x1, [x2, #SW_X29] /* x29=0, x30(lr)=entry */
|
||||
stp xzr, xzr, [x2, #SW_D8]
|
||||
stp xzr, xzr, [x2, #SW_D10]
|
||||
stp xzr, xzr, [x2, #SW_D12]
|
||||
stp xzr, xzr, [x2, #SW_D14]
|
||||
mov x0, x2
|
||||
ret
|
||||
@@ -0,0 +1,275 @@
|
||||
/*
|
||||
StarForth — Steady-State Virtual Machine Runtime
|
||||
Copyright (c) 2023–2025 Robert A. James. All rights reserved.
|
||||
Licensed under the StarForth License, Version 1.0.
|
||||
*/
|
||||
|
||||
/**
|
||||
* timer.c (aarch64) - Timer subsystem using ARM Generic Timer (CNTPCT_EL0)
|
||||
*
|
||||
* Uses the 64-bit system counter available as CNTPCT_EL0. The counter
|
||||
* frequency is read from CNTFRQ_EL0 (set by firmware).
|
||||
*/
|
||||
|
||||
#include "timer.h"
|
||||
#include "console.h"
|
||||
#include "q48_16.h"
|
||||
#include "uefi.h"
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
|
||||
/* ─── ARM generic-timer helpers ─────────────────────────────────────── */
|
||||
|
||||
/* FABRIC-2.md §I.5, 2026-09-04: real hypervisor-vs-hardware detection.
|
||||
* s_cal.vm_mode was hardcoded to 1 unconditionally below (comment:
|
||||
* "QEMU SBSA always uses virtualised Generic Timer") -- true for the
|
||||
* *timing policy* this file cares about, but wrong to reuse as a
|
||||
* general "are we in QEMU" signal elsewhere (contrib-capsule trust-tier
|
||||
* enforcement, §I.5), which is exactly what happened before this was
|
||||
* caught: it would report "always QEMU" on real hardware too.
|
||||
*
|
||||
* ARM has no single CPUID-equivalent hypervisor-present bit the way
|
||||
* amd64's CPUID.1:ECX[31] is (arch/amd64/timer.c's own
|
||||
* running_under_hypervisor()). Checks the ACPI RSDP's OEM ID instead --
|
||||
* "BOCHS " is the SeaBIOS-heritage signature QEMU's ACPI table
|
||||
* generation has used since long before this project, on every machine
|
||||
* type it emulates, aarch64 virt included. Real hardware vendors set
|
||||
* their own OEMID, never this string. Mirrors pci.c's own private Rsdp2
|
||||
* struct layout (signature[8], checksum, oem_id[6]) -- duplicated
|
||||
* rather than shared, same "a few TLV-walking lines is simpler than a
|
||||
* new header" precedent tools/pkcs8_ed25519.c already set. */
|
||||
static int running_under_hypervisor(BootInfo *boot_info) {
|
||||
if (!boot_info || !boot_info->acpi_table) return 0;
|
||||
const uint8_t *rsdp = (const uint8_t *) boot_info->acpi_table;
|
||||
if (memcmp(rsdp, "RSD PTR ", 8) != 0) return 0;
|
||||
return memcmp(rsdp + 9, "BOCHS ", 6) == 0 ? 1 : 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read the AArch64 Physical System Counter with ISB serialisation.
|
||||
*
|
||||
* Issues an @c ISB (Instruction Synchronisation Barrier) before reading
|
||||
* @c CNTPCT_EL0 to ensure all preceding instructions have completed before
|
||||
* the counter value is sampled. This prevents the counter read from being
|
||||
* speculated ahead of a preceding store or flag update, which would produce
|
||||
* an erroneously early timestamp.
|
||||
*
|
||||
* The ISB is heavier than strictly necessary for most timing uses but
|
||||
* provides the same ordering guarantee as @c RDTSCP on x86-64. For
|
||||
* interval measurements where start and end reads are in the same path,
|
||||
* the overhead (1–3 cycles) is negligible.
|
||||
*
|
||||
* @return Current 64-bit @c CNTPCT_EL0 counter value in system-counter ticks.
|
||||
*/
|
||||
static inline uint64_t cntpct_read(void)
|
||||
{
|
||||
uint64_t val;
|
||||
__asm__ volatile ("isb; mrs %0, cntpct_el0" : "=r"(val));
|
||||
return val;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read the AArch64 Counter Frequency Register (@c CNTFRQ_EL0).
|
||||
*
|
||||
* @c CNTFRQ_EL0 is a read-only EL0-accessible register whose value is
|
||||
* written by EL3/EL2 firmware at boot to advertise the system counter
|
||||
* frequency in Hz. It is the architectural way to discover @c CNTPCT_EL0's
|
||||
* tick rate without out-of-band knowledge of the board.
|
||||
*
|
||||
* QEMU's SBSA/virt machine models typically set this to 62,500,000 Hz
|
||||
* (62.5 MHz) for Cortex-A57 compatibility. Real hardware varies widely
|
||||
* (10 MHz on Raspberry Pi 4, 24 MHz on Cortex-A53 dev boards, etc.).
|
||||
* @c timer_init() falls back to 62,500,000 if the register reads zero.
|
||||
*
|
||||
* @return Counter frequency in Hz as set by firmware; 0 if firmware did
|
||||
* not initialise the register (uncommon but possible in bare-metal
|
||||
* bring-up without a proper firmware stack).
|
||||
*/
|
||||
static inline uint64_t cntfrq_read(void)
|
||||
{
|
||||
uint64_t val;
|
||||
__asm__ volatile ("mrs %0, cntfrq_el0" : "=r"(val));
|
||||
return val;
|
||||
}
|
||||
|
||||
/* ─── Module state ───────────────────────────────────────────────────── */
|
||||
|
||||
static uint64_t s_counter_hz = 0; /* CNTFRQ_EL0 (ticks/second) */
|
||||
static uint64_t s_ns_per_tick = 0; /* nanoseconds per counter tick (scaled) */
|
||||
static uint64_t s_base_count = 0; /* counter value at timer_init() */
|
||||
static uint64_t s_base_ns = 0; /* ns offset at timer_init() */
|
||||
|
||||
static timer_calibration_record_t s_cal;
|
||||
|
||||
/* ─── timer_init ─────────────────────────────────────────────────────── */
|
||||
|
||||
/*
|
||||
* @brief Initialise the AArch64 timer subsystem from @c CNTFRQ_EL0 (M5).
|
||||
*
|
||||
* Reads the system counter frequency from @c CNTFRQ_EL0. If firmware left
|
||||
* this register zero (a non-conforming but possible situation in bare-metal
|
||||
* bring-up) the function falls back to 62,500,000 Hz — the canonical
|
||||
* Cortex-A57 / QEMU SBSA frequency.
|
||||
*
|
||||
* Derived values stored in module state:
|
||||
* - @c s_counter_hz — raw frequency in Hz.
|
||||
* - @c s_base_count — @c CNTPCT_EL0 sample at init time; all subsequent
|
||||
* @c timer_now_ns() calls compute elapsed ticks as
|
||||
* @c (cntpct_read() - s_base_count).
|
||||
* - @c s_base_ns — 0 at init; the ns origin for @c timer_now_ns().
|
||||
* - @c s_ns_per_tick — Q16.16 fixed-point nanoseconds per counter tick,
|
||||
* computed as @c (1e9 << 16) / @c freq to avoid floating-point in the
|
||||
* freestanding build. @c timer_now_ns() right-shifts by 16 after the
|
||||
* multiply to recover the integer nanosecond count.
|
||||
*
|
||||
* The calibration record @c s_cal is populated with the firmware-reported
|
||||
* frequency, @c converged = 1, and @c trust = @c TIMER_TRUST_ABSOLUTE
|
||||
* because the ARM Generic Timer is invariant and synchronised by
|
||||
* architecture — no drift-detection loop is needed.
|
||||
*
|
||||
* @param boot_info Kernel @c BootInfo -- GIC base address will be used in a
|
||||
* later milestone for the interrupt controller; as of
|
||||
* 2026-09-04 also consulted here for @c acpi_table, so
|
||||
* @c s_cal.vm_mode can be a real hypervisor-vs-hardware
|
||||
* detection instead of the hardcoded-1 timing-policy
|
||||
* shortcut this field used to double as (see
|
||||
* running_under_hypervisor()'s own doc comment above).
|
||||
* @return 0 always.
|
||||
*/
|
||||
int timer_init(BootInfo *boot_info)
|
||||
{
|
||||
uint64_t freq = cntfrq_read();
|
||||
if (freq == 0) {
|
||||
/* Firmware did not set CNTFRQ; assume 62.5 MHz (Cortex-A57 default) */
|
||||
freq = 62500000ULL;
|
||||
}
|
||||
|
||||
s_counter_hz = freq;
|
||||
s_base_count = cntpct_read();
|
||||
s_base_ns = 0;
|
||||
|
||||
/* ns_per_tick = 1e9 / freq — store as (1e9 << 16) / freq for fixed-point */
|
||||
s_ns_per_tick = (1000000000ULL << 16) / freq;
|
||||
|
||||
s_cal.tsc_hz_mean = freq;
|
||||
s_cal.hpet_hz = 0;
|
||||
s_cal.pit_hz_mean = 0;
|
||||
s_cal.converged = 1;
|
||||
s_cal.vm_mode = running_under_hypervisor(boot_info) ? 1 : 0;
|
||||
s_cal.trust = TIMER_TRUST_ABSOLUTE;
|
||||
|
||||
console_println("Timer: AArch64 generic timer initialised.");
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* ─── timer_tsc_hz ───────────────────────────────────────────────────── */
|
||||
|
||||
/**
|
||||
* @brief Return the system counter frequency in Hz.
|
||||
*
|
||||
* Returns @c s_counter_hz as set from @c CNTFRQ_EL0 by @c timer_init().
|
||||
* If @c timer_init() has not been called yet (or firmware reported 0 and
|
||||
* the fallback was not applied), returns 62,500,000 Hz as a safe default.
|
||||
*
|
||||
* Used by @c apic_timer_init() to compute @c s_timer_period_tsc and by
|
||||
* the shim time backend to convert counter ticks to nanoseconds before
|
||||
* the full timer subsystem is available.
|
||||
*
|
||||
* @return System counter frequency in Hz; at least 62,500,000.
|
||||
*/
|
||||
uint64_t timer_tsc_hz(void)
|
||||
{
|
||||
return s_counter_hz ? s_counter_hz : 62500000ULL;
|
||||
}
|
||||
|
||||
/* ─── timer_now_ns ───────────────────────────────────────────────────── */
|
||||
|
||||
/**
|
||||
* @brief Return a monotonic nanosecond timestamp.
|
||||
*
|
||||
* Reads @c CNTPCT_EL0, computes the delta from @c s_base_count (captured
|
||||
* at @c timer_init()), and converts to nanoseconds using the Q16.16
|
||||
* fixed-point @c s_ns_per_tick:
|
||||
*
|
||||
* @code
|
||||
* ns = s_base_ns + ((delta * s_ns_per_tick) >> 16)
|
||||
* @endcode
|
||||
*
|
||||
* The multiplication uses 64-bit arithmetic; at typical counter frequencies
|
||||
* (≤ 100 MHz) and reasonable uptime intervals (days to weeks) there is no
|
||||
* overflow risk in the delta-to-ns conversion.
|
||||
*
|
||||
* @return Monotonic nanosecond count since @c timer_init(), starting at 0.
|
||||
*/
|
||||
uint64_t timer_now_ns(void)
|
||||
{
|
||||
uint64_t delta = cntpct_read() - s_base_count;
|
||||
/* delta * (1e9 / freq) = (delta * ns_per_tick_q16) >> 16 */
|
||||
return s_base_ns + ((delta * s_ns_per_tick) >> 16);
|
||||
}
|
||||
|
||||
/* ─── timer_check_drift_now ──────────────────────────────────────────── */
|
||||
|
||||
/**
|
||||
* @brief Check for timer drift (AArch64 stub — always returns 0).
|
||||
*
|
||||
* On x86-64 this function cross-checks the TSC against the HPET or PM
|
||||
* Timer to detect frequency drift. The AArch64 Generic Timer is
|
||||
* architecturally invariant and synchronised across all cores in the
|
||||
* system; it cannot drift against itself. This stub always returns 0
|
||||
* (no drift detected) to satisfy the common @c timer_check_drift_now()
|
||||
* call site.
|
||||
*
|
||||
* @return 0 always.
|
||||
*/
|
||||
int timer_check_drift_now(void)
|
||||
{
|
||||
return 0; /* Stub: ARM counter has no drift against itself */
|
||||
}
|
||||
|
||||
/* ─── timer_calibration_record ───────────────────────────────────────── */
|
||||
|
||||
/**
|
||||
* @brief Return a pointer to the timer calibration record.
|
||||
*
|
||||
* Returns @c &s_cal which is populated by @c timer_init() with:
|
||||
* - @c tsc_hz_mean = @c CNTFRQ_EL0 (or 62.5 MHz fallback)
|
||||
* - @c hpet_hz = 0 (no HPET on AArch64)
|
||||
* - @c pit_hz_mean = 0 (no PIT on AArch64)
|
||||
* - @c converged = 1 (Generic Timer is already calibrated by firmware)
|
||||
* - @c vm_mode = real hypervisor-vs-hardware detection as of 2026-09-04
|
||||
* (ACPI RSDP OEM ID check, running_under_hypervisor() above) -- the
|
||||
* Generic Timer itself works identically either way, so this field's
|
||||
* *timing* meaning here is purely informational, unlike amd64 where
|
||||
* vm_mode gates a real calibration-path choice
|
||||
* - @c trust = @c TIMER_TRUST_ABSOLUTE
|
||||
*
|
||||
* The record is exposed to @c kernel_main() and @c timer.h consumers for
|
||||
* boot-log reporting and for the heartbeat subsystem's trust initialisation.
|
||||
*
|
||||
* @return Pointer to the module-static calibration record; valid for the
|
||||
* lifetime of the kernel.
|
||||
*/
|
||||
const timer_calibration_record_t *timer_calibration_record(void)
|
||||
{
|
||||
return &s_cal;
|
||||
}
|
||||
|
||||
/* ─── Heartbeat ──────────────────────────────────────────────────────── */
|
||||
|
||||
/**
|
||||
* @brief Read the raw counter the aarch64 heartbeat is paced against.
|
||||
*
|
||||
* Item 0.8 (FABRIC-0.md §25.1): the shared heartbeat.c now owns
|
||||
* heartbeat_init()/heartbeat_tick()/heartbeat_service()/heartbeat_ticks()/
|
||||
* heartbeat_trust()/heartbeat_state() and the per-arch @c g_heartbeat
|
||||
* state that used to live in this file. This is the one piece that stays
|
||||
* per-architecture -- the same @c CNTPCT_EL0 the rest of this file's
|
||||
* calibration already reads via @c cntpct_read().
|
||||
*
|
||||
* @return Current @c CNTPCT_EL0 value.
|
||||
*/
|
||||
uint64_t heartbeat_read_counter(void)
|
||||
{
|
||||
return cntpct_read();
|
||||
}
|
||||
Reference in New Issue
Block a user