Reorganize source tree: kernel/, v3/, v4/ split and board infrastructure
Source tree reorganization: - Move StarForth v3 engine to v3/ (src/, include/, Makefile) - Move kernel to kernel/ (src/, include/, linker/, Makefile) - Create v4/ skeleton for F18-ISA golden model (DECOMPOSITION.md, JUSTIFICATION.md) - Move FABRIC-0..4.md to docs/fabric/ - Move ONTOLOGY.md and ROADMAP.md to docs/ Board infrastructure: - Add boards/ser5/, boards/raspi/, boards/milkv/, boards/zynq7020/ - Each board has board.mk (ISA, CPU flags, boot recipe) and README.md - Root Makefile becomes thin dispatcher: boot_image, all, clean, docs take TARGET - make boot_image TARGET=SER5|RASPI|MILKV builds one GPT/MBR image per board - ZYNQ7020 target exists but stops with clear error (ARMv7 port not built yet) - scripts/mkdiskimage.sh builds disk images for all boards Docs pipeline: - docs/book/ with LaTeX master (main.tex) and Makefile - pandoc converts Markdown to LaTeX at build time - Two Lua filters: table-widths.lua (wide tables wrap), code-breaks.lua (inline code breaks) - make docs builds single PDF (754 pages, 0 missing characters) - make docs TARGET=<board> adds board appendix - build/docs/<book|board>/meta.tex stamps git commit into PDF Bug fixes: - 42 include paths that only worked by accident now use correct relative paths - clang-18 hardcode replaced with configurable CC variable (fixed aarch64 build) - Pi 5: kernel_2712.img linked at 0x80000, .bss zeroed, memory reserved - Doxyfile, .clang-tidy, README.md, Kconfig paths updated Verified: - Hosted v3 build passes 1012 tests, 0 failures - SER5 image boots in QEMU (OVMF), POST passes, K exact (65536 = Q48_ONE) - Milk-V image boots in QEMU (OpenSBI + U-Boot + bootefi), POST passes - make clean TARGET=<board> removes only that board and its ISA objects - make all builds all boards, hosted v3, and docs in one run Co-authored-by: Junie <junie@jetbrains.com>
This commit is contained in:
rajames
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/*
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StarForth — Steady-State Virtual Machine Runtime
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Copyright (c) 2023–2025 Robert A. James
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All rights reserved.
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This file is part of the StarForth project.
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Licensed under the StarForth License, Version 1.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at:
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https://github.com/star.4th@proton.me/StarForth/LICENSE.txt
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This software is provided "AS IS", WITHOUT WARRANTY OF ANY KIND,
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express or implied, including but not limited to the warranties of
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merchantability, fitness for a particular purpose, and noninfringement.
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See the License for the specific language governing permissions and
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limitations under the License.
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StarForth — Steady-State Virtual Machine Runtime
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Copyright (c) 2023–2025 Robert A. James
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All rights reserved.
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This file is part of the StarForth project.
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Licensed under the StarForth License, Version 1.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at:
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https://github.com/star.4th@proton.me/StarForth/LICENSE.txt
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This software is provided "AS IS", WITHOUT WARRANTY OF ANY KIND,
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express or implied, including but not limited to the warranties of
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merchantability, fitness for a particular purpose, and noninfringement.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* arch.c (amd64) - Architecture abstractions for StarKernel on x86_64
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*/
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#include "arch.h"
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#include <stdint.h>
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/*
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* GDT entries for 64-bit mode.
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* In long mode, the base and limit fields of code/data segments are ignored,
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* but the access and flags bytes must be correct.
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*/
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struct gdt_entry {
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uint16_t limit_low;
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uint16_t base_low;
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uint8_t base_mid;
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uint8_t access;
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uint8_t granularity; /* includes high nibble of limit */
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uint8_t base_high;
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} __attribute__((packed));
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struct gdtr {
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uint16_t limit;
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uint64_t base;
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} __attribute__((packed));
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/*
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* GDT layout:
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* 0x00: Null descriptor
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* 0x08: 64-bit kernel code segment (selector used in IDT)
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* 0x10: Kernel data segment
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*/
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static struct gdt_entry gdt[3] __attribute__((aligned(16)));
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/**
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* @brief Populate a GDT entry with limit 0xFFFF and a zero base.
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*
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* In 64-bit long mode the base and limit fields of code/data segment
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* descriptors are ignored by the processor; only the @p access and
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* @p granularity flag bytes are architecturally significant. This helper
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* writes the canonical long-mode descriptor layout: limit = 0xFFFF, all base
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* bytes = 0, then stores the provided access and granularity values.
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*
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* @param index Index into the @c gdt[] array (0 = null, 1 = code, 2 = data).
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* @param access Access byte (e.g., 0x9A for kernel code, 0x92 for data).
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* @param granularity Granularity/flags byte (e.g., 0x20 sets the L-bit for 64-bit code).
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*/
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static void gdt_set_entry(int index, uint8_t access, uint8_t granularity)
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{
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gdt[index].limit_low = 0xFFFF;
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gdt[index].base_low = 0;
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gdt[index].base_mid = 0;
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gdt[index].access = access;
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gdt[index].granularity = granularity;
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gdt[index].base_high = 0;
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}
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/**
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* @brief Initialise and load the minimal 3-entry GDT required for long mode.
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*
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* Builds three GDT entries in the @c gdt[] array and loads the descriptor via
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* @c LGDT followed by a far-return sequence to reload @c CS to selector 0x08
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* and all other segment registers to 0x10:
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*
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* - Slot 0 (0x00): Null descriptor — all fields zero.
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* - Slot 1 (0x08): 64-bit kernel code (access=0x9A, granularity=0x20).
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* - Slot 2 (0x10): Kernel data (access=0x92, granularity=0x00).
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*
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* Must be called before @c arch_interrupts_init() because the IDT uses
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* selector 0x08 for all gate descriptors.
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*/
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static void gdt_init(void)
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{
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/* Null descriptor */
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gdt[0].limit_low = 0;
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gdt[0].base_low = 0;
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gdt[0].base_mid = 0;
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gdt[0].access = 0;
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gdt[0].granularity = 0;
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gdt[0].base_high = 0;
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/*
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* 64-bit kernel code segment (selector 0x08)
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* Access: 0x9A = Present (1), DPL 0 (00), S=1 (code/data), Exec (1), Conforming (0), Readable (1), Accessed (0)
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* Granularity: 0x20 = Long mode (L=1), Default operand size (D=0, must be 0 for long mode)
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*/
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gdt_set_entry(1, 0x9A, 0x20);
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/*
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* Kernel data segment (selector 0x10)
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* Access: 0x92 = Present (1), DPL 0 (00), S=1 (code/data), Exec (0), Direction (0), Writable (1), Accessed (0)
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* Granularity: 0x00 (no special flags for data segment)
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*/
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gdt_set_entry(2, 0x92, 0x00);
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struct gdtr gdtr_val;
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gdtr_val.limit = sizeof(gdt) - 1;
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gdtr_val.base = (uint64_t)&gdt[0];
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__asm__ volatile (
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"lgdt %0\n\t"
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"pushq $0x08\n\t" /* Push new CS */
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"leaq 1f(%%rip), %%rax\n\t" /* Load address of label 1 */
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"pushq %%rax\n\t" /* Push return address */
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"lretq\n\t" /* Far return to reload CS */
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"1:\n\t"
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"mov $0x10, %%ax\n\t" /* Load new DS/ES/SS/FS/GS */
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"mov %%ax, %%ds\n\t"
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"mov %%ax, %%es\n\t"
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"mov %%ax, %%ss\n\t"
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"mov %%ax, %%fs\n\t"
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"mov %%ax, %%gs\n\t"
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:
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: "m"(gdtr_val)
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: "rax", "memory"
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);
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}
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/**
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* @brief Perform the earliest x86-64 architecture initialisation.
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*
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* Called immediately after the UEFI boot stub transfers control to the
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* kernel, before the console or interrupt controller are available.
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* Loads the minimal three-entry GDT via @c gdt_init() so that subsequent
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* code has valid segment selectors. IDT setup is deferred until after the
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* console is live (called separately via @c arch_interrupts_init()).
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*/
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void arch_early_init(void)
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{
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gdt_init(); /* Must be done before IDT, since IDT uses selector 0x08 */
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/* IDT setup is done later via arch_interrupts_init() after console is live */
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}
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/**
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* @brief Enable hardware interrupts on the current CPU core (x86-64 STI).
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*
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* Issues the @c STI instruction to set the Interrupt Flag. Must be called
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* after the IDT is loaded and the APIC is configured, otherwise the first
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* interrupt will triple-fault.
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*/
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void arch_enable_interrupts(void)
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{
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__asm__ volatile ("sti");
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}
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/**
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* @brief Disable hardware interrupts on the current CPU core (x86-64 CLI).
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*
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* Issues the @c CLI instruction to clear the Interrupt Flag. Used around
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* critical sections in the single-threaded kernel where interrupt delivery
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* would corrupt shared state.
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*/
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void arch_disable_interrupts(void)
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{
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__asm__ volatile ("cli");
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}
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/**
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* @brief Halt the CPU until the next interrupt (x86-64 HLT).
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*
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* Issues the @c HLT instruction. In the kernel panic path this is called
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* in an infinite loop (interrupts disabled) to stop the processor permanently.
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* In normal use it is called once per idle iteration to reduce power consumption.
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*/
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void arch_halt(void)
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{
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__asm__ volatile ("hlt");
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}
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void arch_cold_reset(void)
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{
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arch_disable_interrupts();
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/* Pulse keyboard controller reset line — standard bare-metal amd64 reset */
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__asm__ volatile ("outb %0, %1" : : "a"((uint8_t)0xFE), "Nd"((uint16_t)0x64));
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/* Should not reach here; spin as fallback */
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for (;;) __asm__ volatile ("cli; hlt");
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}
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/**
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* @brief Read the x86-64 Time Stamp Counter (RDTSC).
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*
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* Executes @c RDTSC and combines @c EDX:EAX into a 64-bit value. Does not
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* serialise instruction execution; use @c RDTSCP or a surrounding @c CPUID
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* where ordering guarantees are required.
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*
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* @return Current TSC value in CPU cycles.
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*/
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uint64_t arch_read_timestamp(void)
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{
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uint32_t lo, hi;
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__asm__ volatile ("rdtsc" : "=a"(lo), "=d"(hi));
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return ((uint64_t)hi << 32) | lo;
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}
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/**
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* @brief Initialise the x86-64 MMU (stub — deferred to a later milestone).
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*
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* Full four-level page table setup is deferred; the VMM subsystem
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* (@c vmm.c) handles page table management independently. This function
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* exists as an architectural hook for future per-CPU MMU configuration
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* that must run after GDT/IDT setup but before the first memory access
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* through a non-identity-mapped virtual address.
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*/
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void arch_mmu_init(void)
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{
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/* Stub: paging will be wired up in later milestones */
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}
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