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Checkpoint: paired ACL-TTL overhead measurement, 12/18 cells (2/3)

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Cells 10-12 complete and verified (480/480 rows, 16/16 cfg coverage,
zero errors each): amd64/67890 enabled, riscv64/13579 enabled,
riscv64/67890 disabled.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
This commit is contained in:
Robert Allan James
2026-08-20 19:03:37 -04:00
co-authored by Claude Sonnet 5
parent 1880e78a1a
commit becae2a763
8 changed files with 49852 additions and 0 deletions
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experiments/bare_metal/runs/acl-ttl-overhead-20260820/amd64-seed67890-enabled.csv
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experiments/bare_metal/runs/acl-ttl-overhead-20260820/riscv64-seed13579-enabled.csv
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File diff suppressed because it is too large Load Diff
experiments/bare_metal/runs/acl-ttl-overhead-20260820/riscv64-seed67890-disabled.csv
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experiments/bare_metal/runs/acl-ttl-overhead-20260820/timing.csv
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@@ -8,3 +8,6 @@ order,arch,seed,acl,start_ts,end_ts,elapsed_s,rows,cfgs_ok,errors
7,aarch64,13579,enabled,1787264974.177469213,1787265291.239105652,317.062,480,TRUE,0
8,amd64,13579,disabled,1787265488.338670740,1787265680.056553038,191.718,480,TRUE,0
9,amd64,12345,disabled,1787265875.831736966,1787266064.967044192,189.135,480,TRUE,0
10,amd64,67890,enabled,1787266216.072579477,1787266416.714834209,200.642,480,TRUE,0
11,riscv64,13579,enabled,1787266537.716776416,1787266701.705197579,163.988,480,TRUE,0
12,riscv64,67890,disabled,1787266808.730892518,1787266975.164517195,166.434,480,TRUE,0
1 order arch seed acl start_ts end_ts elapsed_s rows cfgs_ok errors
8 7 aarch64 13579 enabled 1787264974.177469213 1787265291.239105652 317.062 480 TRUE 0
9 8 amd64 13579 disabled 1787265488.338670740 1787265680.056553038 191.718 480 TRUE 0
10 9 amd64 12345 disabled 1787265875.831736966 1787266064.967044192 189.135 480 TRUE 0
11 10 amd64 67890 enabled 1787266216.072579477 1787266416.714834209 200.642 480 TRUE 0
12 11 riscv64 13579 enabled 1787266537.716776416 1787266701.705197579 163.988 480 TRUE 0
13 12 riscv64 67890 disabled 1787266808.730892518 1787266975.164517195 166.434 480 TRUE 0