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Robert Allan JamesandClaude Sonnet 5 5f4df673c1 riscv64: PLIC bring-up, external-interrupt substrate (item 4.3.5b)

Punch list §25 item 4.3.5b complete.

sie.SEIE enabled, PLIC threshold/claim/complete wired into the trap
handler. Verified with a UART-loopback synthetic interrupt (PLIC has no
software set-pending register, unlike GICv2): claim_count=1, last_irq=10,
IIR confirms genuine receive-data cause, byte matched exactly. Self-test
code run once for evidence then fully reverted, per Captain Bob's ruling;
only the permanent substrate remains, no source enabled by default.
Three-arch acceptance boot clean, zero exceptions.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>

2026-08-08 11:24:47 -04:00

apic.c

riscv64: PLIC bring-up, external-interrupt substrate (item 4.3.5b)

2026-08-08 11:24:47 -04:00

arch.c

riscv64: explicit Bare-mode satp switch (item 4.3.5a)

2026-08-08 11:07:29 -04:00

boot.S

Initial commit — LithosAnanke kernel

2026-08-01 07:49:56 -04:00

interrupts.c

riscv64: PLIC bring-up, external-interrupt substrate (item 4.3.5b)

2026-08-08 11:24:47 -04:00

isr.S

riscv64: real trap entry with save/restore and SRET return

2026-08-03 12:52:34 -04:00

kernel_entry.S

Fix riscv64 boot crash: add missing kernel stack trampoline

2026-08-02 06:59:48 -04:00

plic.c

riscv64: PLIC bring-up, external-interrupt substrate (item 4.3.5b)

2026-08-08 11:24:47 -04:00

README.md

Initial commit — LithosAnanke kernel

2026-08-01 07:49:56 -04:00

timer.c

starkernel: converge the tick path and wire the adaptive heartbeat (item 0.8)

2026-08-04 00:01:48 -04:00

README.md

src/starkernel/arch/riscv64/

RISC-V 64-bit architecture support for LithosAnanke.

arch.c — architecture init entry point.
apic.c — PLIC (Platform-Level Interrupt Controller) stub, named apic.c to match the shared per-arch file-naming convention across amd64/aarch64/riscv64 (RISC-V has no Local APIC). Satisfies the common apic_init()/EOI call sites without real PLIC bring-up yet; deferred to a later milestone.
timer.c — timer setup (heartbeat tick source).
interrupts.c — trap vector setup and interrupt dispatch.
boot.S — early boot assembly.
isr.S — interrupt service routine stubs.

No kernel_entry.S — see Makefile.starkernel for how the riscv64 loader image is produced (ELF → scripts/gen_pe_reloc.py-patched relocations → objcopy → PE).