Files

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rajamesandClaude Opus 5.5 0e2c60dac3 fix(raspi): the Pi 5's native path turns the MMU and caches on before any C; bounded mailbox; framebuffer address from dma-ranges

boards/BRINGUP.md R2/R3, FABRIC-3 SXXXIX.  The entry stub cleans the cache
over the image, builds an identity map (the image's GiB Normal, the rest
Device) and enables MMU and caches at EL2 (or EL1); rpi5_mmu.c makes the
devicetree's RAM Normal and the framebuffer uncached.  Mailbox waits give
up after one second; the buffer is cleaned around the exchange; the
framebuffer address goes through dma-ranges, not a Pi 4 mask.

New rpi5-rehearsal target runs the native image on QEMU virt at EL2.  It
found three more that would each have stopped the board: the PL011 shift
(mine, c9519173; the host test asserted it), the GIC address not carried
through /soc's ranges (new fdt_reg_address(), checked against the real
Pi 5 DTB), and no timer IRQ at EL2 (HCR_EL2.IMO/FMO/AMO).

Rehearsal: POST 1052 passed, same parity hash as UEFI.  Standard acceptance
on three ISAs: POST 1052, hash 0x82f4ae7cb2e2d424.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

2026-10-14 12:58:35 -04:00

apic.c

fix(raspi): the Pi 5's native path turns the MMU and caches on before any C; bounded mailbox; framebuffer address from dma-ranges

2026-10-14 12:58:35 -04:00

arch.c

Reorganize source tree: kernel/, v3/, v4/ split and board infrastructure

2026-10-01 15:40:09 -04:00

boot.S

Reorganize source tree: kernel/, v3/, v4/ split and board infrastructure

2026-10-01 15:40:09 -04:00

interrupts.c

Reorganize source tree: kernel/, v3/, v4/ split and board infrastructure

2026-10-01 15:40:09 -04:00

isr.S

Reorganize source tree: kernel/, v3/, v4/ split and board infrastructure

2026-10-01 15:40:09 -04:00

native_rpi5_entry.S

fix(raspi): the Pi 5's native path turns the MMU and caches on before any C; bounded mailbox; framebuffer address from dma-ranges

2026-10-14 12:58:35 -04:00

README.md

Reorganize source tree: kernel/, v3/, v4/ split and board infrastructure

2026-10-01 15:40:09 -04:00

rpi5_dtb.c

Reorganize source tree: kernel/, v3/, v4/ split and board infrastructure

2026-10-01 15:40:09 -04:00

rpi5_mailbox.c

fix(raspi): the Pi 5's native path turns the MMU and caches on before any C; bounded mailbox; framebuffer address from dma-ranges

2026-10-14 12:58:35 -04:00

rpi5_mmu.c

fix(raspi): the Pi 5's native path turns the MMU and caches on before any C; bounded mailbox; framebuffer address from dma-ranges

2026-10-14 12:58:35 -04:00

rpi5_native_boot.c

fix(raspi): the Pi 5's native path turns the MMU and caches on before any C; bounded mailbox; framebuffer address from dma-ranges

2026-10-14 12:58:35 -04:00

switch.S

Reorganize source tree: kernel/, v3/, v4/ split and board infrastructure

2026-10-01 15:40:09 -04:00

timer.c

Reorganize source tree: kernel/, v3/, v4/ split and board infrastructure

2026-10-01 15:40:09 -04:00

README.md

src/starkernel/arch/aarch64/

AArch64 architecture support for LithosAnanke.

arch.c — architecture init entry point.
apic.c — GIC (Generic Interrupt Controller) stub, named apic.c to match the shared per-arch file-naming convention across amd64/aarch64/riscv64. Satisfies the common apic_init()/apic_eoi() call sites without real GIC bring-up yet; deferred to a later milestone.
timer.c — architected timer setup (heartbeat tick source).
interrupts.c — exception vector table setup and interrupt dispatch.
boot.S — early boot assembly.
isr.S — interrupt service routine stubs.

No kernel_entry.S — aarch64 uses a different UEFI loader entry path (clang/lld-link COFF target, since GCC cannot produce an aarch64 PE image; see Makefile.starkernel).