Robert Allan JamesandClaude Sonnet 5
986d042aa7
Fourth stage of the preemptive context-switching plan, and the biggest. LithosAnanke now genuinely, continuously preempts between Hera, Hermes, and Artemis -- timer-driven, running live for the entire remainder of every boot once the Tripod fleet registers, not a bounded probe. A real design fork was resolved before writing code: the naive approach (the timer ISR calling Stage 2's sk_vm_context_switch() directly) is broken -- Stage 0's trap frame lives on whatever stack was active at interrupt time, and jumping to a different stack via Stage 2's own independent swap mid-handler would abandon that trap frame unresumed, guaranteed corruption on the first tick. Chose the safer of two named options: the ISR only ever sets a flag and returns completely normally through its own full epilogue; the actual switch happens moments later, via Stage 2's already-proven mechanism, at a safe cooperative checkpoint on the mainline (execute_colon_word()'s per-word dispatch loop, checked on literally every word, not throttled to the existing 256-word heartbeat-tuning cadence) -- confirmed with the user that word-level granularity is fine-grained enough given the eventual Zynq FPGA target where a word is a mnemonic. New capsule_vm_switch_signal.c/.h: a purpose-built run-readiness signal, deliberately separate from capsule_vm_physics.c's execution-heat engine (that one's own header documents itself as never touched from interrupt context, by design). Slot table sized with headroom (8) rather than hardcoded to today's 3 participants, so extending participation later is another register() call, not a redesign -- per direct request to leave room for swapping the participant set. Simple linear accumulate-then- threshold for this first cut; a fancier law can replace it later without touching the mechanism around it. heartbeat_tick() gains its one deliberate, documented amendment to this file's own top-half/bottom-half discipline -- the first time this codebase reaches into VM-scheduling state from real ISR context. Registration happens only after all three VMs are fully born, right before the REPL starts -- no critical-section protection yet against being switched away mid-birth-setup. Known, flagged rough edge (not reconciled this pass): MSG-TICK's own idle-pump and this new mechanism can still independently move control between the same VMs; not observed to interact badly in verification, but not fully unified either. Verified interactively at the console on all 3 architectures with continuous background preemption running throughout -- amd64 computed `1 1 + .` -> 2, aarch64 computed `1 1 + dup DUP * . CR` -> 4, both correct, REPL fully responsive, zero fault indicators over sustained runtime. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_016UNhH1mhi52i6Qihh7ZV5S
src/starkernel/
LithosAnanke — the bare-metal UEFI kernel that boots StarForth directly on
hardware (amd64/aarch64/riscv64). Built only via Makefile.starkernel; the
only valid acceptance test is the three-arch QEMU boot (see
.claude/CLAUDE.md), never make test.
kernel_main.c— kernel entry point, driving the boot milestones (console init, PMM, VMM, interrupts, timers, kmalloc heap, VM bootstrap).repl.c— kernel REPL.doe_log.c— kernel-side DoE (Design of Experiments) metrics logging.
Subdirectories:
arch/{amd64,aarch64,riscv64}/— per-architecture support (APIC/GIC/ PLIC interrupt controller, timers, boot/ISR assembly).boot/— UEFI loader, ELF loading, kernel command-line parsing.capsule/— capsule birth/run/load/validate pipeline.hal/— hardware-abstraction-layer implementation (console, framebuffer, VT100, memory, host services).hash/— XXHash64 content-addressing implementation.math/— kernel-build Q48.16 fixed-point arithmetic.memory/— physical/virtual memory managers and the kernel heap.pci/— PCI bus enumeration.virtio/— VirtIO block device driver.vm/— kernel VM subsystem (bootstrap, core interpreter, parity logging, capsule arena).
See include/starkernel/README.md for the corresponding headers.