Claude
3bd81097e1
The header scan (Captain Bob, 2026-11-10): 788 source files -- 351 with the
SL-1.0 header, 12 with the old name (docs/working/experiments, kept by
ruling), 31 under someone else's licence (tools/kconfig, Linux's, GPL-2.0:
kept), and 394 with none. Ruled: the SPDX form; capsules (.4th, .f18) and
proofs (.thy) left for a ruling of their own (mkcapsule's 64x16 block format,
content-addressed capsules).
253 files now begin
SPDX-License-Identifier: LicenseRef-Starship-1.0
Copyright (c) 2023-2026 Robert A. James
as a /* */ block (C, headers, assembly, linker scripts) or # lines (scripts,
Makefiles, Kconfig; below a shebang or a coding line); tools/mkcapsule.c,
which had the copyright line, gets the SPDX line only.
Not touched: docs/working/ (archive and old campaign material, as the
ruling kept the experiments); v4/system/post_cases.c (generated by
v4/tools/mkpost.py, "do not edit" -- the generator has the header).
Comments only: the kernel builds on amd64, aarch64, riscv64; make -C v4
test-32: 39 programs, 0 failures; every changed script parses.
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01GE3SDvQn5EoxdGufk84zz2
Xilinx Zynq-7020 boot media
The Zynq-7020's processing system is a dual Cortex-A9: ARMv7-A, 32-bit. It is the host for the
StarForth v4 mesh (docs/v4.0.0/JUSTIFICATION.md §5, §8).
Boot chain: BootROM, then BOOT.BIN (U-Boot SPL with the board's ps7_init DDR and clock setup),
then U-Boot, then LithosAnanke. Everything is read from the SD card's FAT partition.
Status: no image yet. make boot_image TARGET=ZYNQ7020 stops with an error, because there is no
ARMv7 kernel port (kernel/src/arch/armv7: entry code, MMU, GIC, private timer). A trial
compile for Cortex-A9 built 147 of the 151 kernel and engine sources. The four that failed use
__int128 or have no ARMv7 branch: kernel/src/crypto/fe25519.c,
kernel/src/crypto/scalar25519.c, kernel/src/hal/hal.c and
v3/src/word_source/mixed_arithmetic_words.c.
BOOT.BIN depends on the exact board, because ps7_init holds that board's DDR timing.
The board: Puzhi PZ-StarLite (recorded 2026-10-28)
Captain Bob's board is a Puzhi (璞致) PZ-StarLite, Zynq-7020. From its hardware user manual and schematic (vendor material, not in this repo; see below):
| What | On the board |
|---|---|
| JTAG | On board: an FTDI FT232HL with a 93LC56B EEPROM, on its own USB-C port. FT232H JTAG is what the open-source tools drive (openFPGALoader, OpenOCD's ftdi driver): no adapter and no AMD tools. Expect FTDI 0403:6014 in lsusb. |
| Power | That same USB-C cable ("one cable for power and JTAG"), or 5 V on the 40-pin header -- one or the other. |
| Serial console | On board: a CH340E USB-UART on a second USB-C port, 3.3 V, to the PS UART (TX MIO11, RX MIO10). Linux's ch341 driver: /dev/ttyUSB0. |
| Boot mode | A jumper: JTAG, QSPI flash or SD card. |
| Ethernet | Two gigabit ports, RTL8211F over RGMII: one on the PS, one on the PL. |
| HDMI | Wired to the PL (bank 34): it shows nothing until a PL design drives it. |
| USB | A USB 2.0 host port (USB3320C PHY on the PS). |
| Memory | DDR3 on the PS. |
The bench needs only cables: two USB-C data cables (JTAG and power; serial), a microSD card and a reader, an Ethernet cable; a powered hub if a PC port cannot power the board.
The vendor's files are on Captain Bob's machine beside this checkout, in ~/CLionProjects/:
03.开机测试--Boot Test/ (a working BOOT.BIN and image.ub for this board -- its first-stage
loader carries this board's ps7_init), 04.硬件相关--Hardware/ (schematic, connector pin table,
form factor), 05.教程和源码--Course_Demos/ (the hardware user manual; FPGA, SDK, Linux, HLS and
PYNQ demos as .rar archives -- 2_SDK.rar is the likely home of ps7_init.c, not yet opened),
02.软件和驱动--Software Tools and Drivers/ (FTDI and CH341 drivers, PetaLinux installers).
Reusing the vendor's generated ps7_init is the route to a PS initialised without running
Vivado (no AMD tools, Captain Bob's ruling).