Source tree reorganization: - Move StarForth v3 engine to v3/ (src/, include/, Makefile) - Move kernel to kernel/ (src/, include/, linker/, Makefile) - Create v4/ skeleton for F18-ISA golden model (DECOMPOSITION.md, JUSTIFICATION.md) - Move FABRIC-0..4.md to docs/fabric/ - Move ONTOLOGY.md and ROADMAP.md to docs/ Board infrastructure: - Add boards/ser5/, boards/raspi/, boards/milkv/, boards/zynq7020/ - Each board has board.mk (ISA, CPU flags, boot recipe) and README.md - Root Makefile becomes thin dispatcher: boot_image, all, clean, docs take TARGET - make boot_image TARGET=SER5|RASPI|MILKV builds one GPT/MBR image per board - ZYNQ7020 target exists but stops with clear error (ARMv7 port not built yet) - scripts/mkdiskimage.sh builds disk images for all boards Docs pipeline: - docs/book/ with LaTeX master (main.tex) and Makefile - pandoc converts Markdown to LaTeX at build time - Two Lua filters: table-widths.lua (wide tables wrap), code-breaks.lua (inline code breaks) - make docs builds single PDF (754 pages, 0 missing characters) - make docs TARGET=<board> adds board appendix - build/docs/<book|board>/meta.tex stamps git commit into PDF Bug fixes: - 42 include paths that only worked by accident now use correct relative paths - clang-18 hardcode replaced with configurable CC variable (fixed aarch64 build) - Pi 5: kernel_2712.img linked at 0x80000, .bss zeroed, memory reserved - Doxyfile, .clang-tidy, README.md, Kconfig paths updated Verified: - Hosted v3 build passes 1012 tests, 0 failures - SER5 image boots in QEMU (OVMF), POST passes, K exact (65536 = Q48_ONE) - Milk-V image boots in QEMU (OpenSBI + U-Boot + bootefi), POST passes - make clean TARGET=<board> removes only that board and its ISA objects - make all builds all boards, hosted v3, and docs in one run Co-authored-by: Junie <junie@jetbrains.com>
64 lines
2.5 KiB
C
64 lines
2.5 KiB
C
/*
|
||
StarForth — Steady-State Virtual Machine Runtime
|
||
Copyright (c) 2023–2025 Robert A. James. All rights reserved.
|
||
Licensed under the StarForth License, Version 1.0.
|
||
*/
|
||
|
||
/**
|
||
* plic.h - Platform-Level Interrupt Controller interface (riscv64 only)
|
||
*
|
||
* Item 4.3.5a (FABRIC-0.md §27.5): Phase 0 (0.2/0.3) only ever enabled the
|
||
* S-mode *timer* interrupt (sie.STIE). External interrupts (sie.SEIE) were
|
||
* never touched, and the PLIC -- the only external-interrupt path on
|
||
* RISC-V, there is no legacy PIC or I/O APIC equivalent -- had no driver
|
||
* at all before this item. Pure substrate: this item wires the mechanism
|
||
* (claim/dispatch/complete) with no permanent source enabled by default;
|
||
* a real consumer (4.3.5b, virtio-keyboard) enables its own source later.
|
||
*
|
||
* @c plic_init() takes the boot DTB as of FABRIC-3.md §V.3 item 3's fix,
|
||
* 2026-09-05: the base address was previously a QEMU-virt-specific
|
||
* hardcoded constant, unconditionally wrong on the Milk-V Mars's real
|
||
* JH7110 PLIC. See @c plic.c's file header for the discovery mechanism.
|
||
*/
|
||
|
||
#ifndef STARKERNEL_PLIC_H
|
||
#define STARKERNEL_PLIC_H
|
||
|
||
#include <stdint.h>
|
||
|
||
/**
|
||
* Map the PLIC and set the S-mode hart-0 context's priority threshold to 0
|
||
* (maximally permissive -- safe because nothing is enabled at any source
|
||
* by default; enabling a source is what actually lets it reach claim()).
|
||
* Also sets sie.SEIE. Does not touch sstatus.SIE -- arch_enable_interrupts()
|
||
* still owns that, same as the timer.
|
||
*
|
||
* @param dtb Candidate devicetree blob (@c BootInfo->dtb); NULL-safe. When
|
||
* a real @c "sifive,plic-1.0.0" node is found, the PLIC base
|
||
* address is read from its @c reg property; otherwise falls
|
||
* back to the QEMU-virt-machine constant, unchanged from this
|
||
* function's previous unconditional behaviour.
|
||
* @return 0 on success.
|
||
*/
|
||
int plic_init(const void *dtb);
|
||
|
||
/** Set a source's interrupt priority (1-7; 0 means "never interrupt"). */
|
||
void plic_set_priority(uint32_t irq, uint32_t priority);
|
||
|
||
/** Enable a source for the S-mode hart-0 context. */
|
||
void plic_enable(uint32_t irq);
|
||
|
||
/** Disable a source for the S-mode hart-0 context. */
|
||
void plic_disable(uint32_t irq);
|
||
|
||
/**
|
||
* Claim the highest-priority pending interrupt for the S-mode hart-0
|
||
* context. Returns the source ID, or 0 if none is pending.
|
||
*/
|
||
uint32_t plic_claim(void);
|
||
|
||
/** Signal completion of the source previously returned by plic_claim(). */
|
||
void plic_complete(uint32_t irq);
|
||
|
||
#endif /* STARKERNEL_PLIC_H */
|